Configuring the Altlvds RX Megafunction in 14 bit device mode

[johnt2]

Hello,

I am looking for guidance or an example design that explains configuring the ALTLVDS RX megafunction for use with a TI 14 bit LVDS ADC. The ADC has 16 LVDS channels, 1 bit clock (DDR) and 1 framing bit. We are using an Arria 10 SOC. I found a youtube video online, but as mentioned in another community post below, the reference material does not appear to be available. I currently have the ALTLVDS block configured for 7 bit operation and concatenate the two 7 bit captures, I am not sure how to manage the DDR clock and framing bit. ADC timing diagram is shown below:

Thanks

 

https://community.intel.com/t5/FPGA-Intellectual-Property/Altlvds-RX-Megafunction-in-14-bit-device-mode/m-p/1206521

[johnt2]

This post offers a method of handling the frame bit, but not the DDR clock.

https://community.intel.com/t5/FPGA-Intellectual-Property/to-use-altlvds-how-I-can-use-LVDS-bit-clock-and-LVDS-frame-clock/m-p/133573

[AqidAyman_Intel]

I believe you can refer to the Handbook available on below link for the guideline of the clocking the differential receivers in Arria 10 device. You can also check the section content and related information provided in the link:

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/clocking-differential-receivers.html