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Connect PCIe to Nios II (MegaWizard to SOPC-Builder) [for root-port]

Honored Contributor II



I want to implement a PCI-Express root-port (for one endpoint) on a Cyclone IV-FPGA with an µClinux as OS and the Altera Nios II as CPU. The main-components of the system are the Nios II-processor, a DDR2-SDRAM and the PCIe-module. Of course, I have to implement the device driver for the PCIe-subsystem running on the embedded Linux. But this problem is the smaller one. 


Due to the fact, that I am needing the root-port-functionality, I have to generate the PCIe-module with the MegaWizard Plug-In Manager. My current problem is to connect the PCIe Hard-IP (generated by the MegaWizard) with the Nios II, respectively the DDR2-SDRAM (both generated with the SOPC-Builder). 


Does anybody know about a reference design for the Cyclone IV FPGA-family, that shows how to connect a PCIe-HIP (MegaWizard) with a SOPC-Project? Additionally I would like to know, if there are any reference designs or design examples for a root-port including the application-core logic. Or maybe you could help me in any other way? 


Thank you for every hint! 




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Honored Contributor II

Hi please do you move forward? 

because I have the same problem like you: 

To understand how any Design under Cyclone IV works afterwards to implement additional interfaces ..... 


Please your advice could be helpful