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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Connections for soft PCIe

Honored Contributor II

In the first stage, I followed the instructions in the document "An SOPC Builder PCI Express Design with GUI Interface an532.pdf". But in our project CycloneIVE is using and I generated soft PCIe. As a result, the program has created a component: 

component mpciess is  

port ( 

-- 1) global signals: 

signal clk_0 : in std_logic; 

signal reset_n : in std_logic; 

-- the_pcie_compiler_0 

signal clk125_out_pcie_compiler_0 : out std_logic; 

signal pcie_rstn_pcie_compiler_0 : in std_logic; 

signal phystatus_ext_pcie_compiler_0 : in std_logic; 

signal pipe_rstn_pcie_compiler_0 : out std_logic; 

signal pipe_txclk_pcie_compiler_0 : out std_logic; 

signal powerdown_ext_pcie_compiler_0 : out std_logic_vector (1 downto 0); 

signal refclk_pcie_compiler_0 : in std_logic; 

signal rxdata0_ext_pcie_compiler_0 : in std_logic_vector (7 downto 0); 

signal rxdatak0_ext_pcie_compiler_0 : in std_logic; 

signal rxelecidle0_ext_pcie_compiler_0 : in std_logic; 

signal rxpolarity0_ext_pcie_compiler_0 : out std_logic; 

signal rxstatus0_ext_pcie_compiler_0 : in std_logic_vector (2 downto 0); 

signal rxvalid0_ext_pcie_compiler_0 : in std_logic; 

signal test_in_pcie_compiler_0 : in std_logic_vector (31 downto 0); 

signal test_out_pcie_compiler_0 : out std_logic_vector (511 downto 0); 

signal txcompl0_ext_pcie_compiler_0 : out std_logic; 

signal txdata0_ext_pcie_compiler_0 : out std_logic_vector (7 downto 0); 

signal txdatak0_ext_pcie_compiler_0 : out std_logic; 

signal txdetectrx_ext_pcie_compiler_0 : out std_logic; 

signal txelecidle0_ext_pcie_compiler_0 : out std_logic; 

signal xphy_pll_areset_pcie_compiler_0 : in std_logic 


end component mpciess; 

The project has compilation without any errors. 


In which document can I find information on the assignment of these signals? Which of them go on a physical level, and which should be linked to the internal logic? 

Are there any examples for soft PCIe? 


The QSYS program does not support the soft PCIe unfortunately.
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2 Replies
Honored Contributor II

here is the document 



but all these should be connected to your internal logic. this core has nothing to do with software. all "soft" means is that it uses internal logic rather than a dedicated hard IP core.
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Honored Contributor II

Yes, at the soft core I understand that it is generated by the internal logic. Thanks for the link. Yes, this is what I need.

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