FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6569 Discussions

Constraint page in IP toolbench Megawizard

Altera_Forum
Honored Contributor II
‎11-05-2008 10:51 AM
993 Views

Hi There, 

 

I generated the legacy DDR2 controller for StratixIIGX device using Megawizard. There is a constraint page in IP Toolbench. I am not able to understand the various fields on this page. I think that these fields must be constraining the pin assignments for DQ/DQS. I have got cetain pin assignments as per our board. How can I edit this page to constrain the pin assignments for DQ/DQs? Please suggest. 

 

Regards, 

Harsh Bandil
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎11-06-2008 10:26 AM
274 Views

I am able to edit the pin assignments under the assignment tab. But when I regenerate the variation, all the assignments are lost and default pin assignments come into effect. Any thought on it, how can I ensure that edited pin assignments are not lost after regenerating the variation

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.