Converting TSE IP register settings from TCL script to VHDL

[MDehp]

Hi everyone,

I want to use 2 tse MAC's in my own design in HDL-author, but it seems somehow that the registers that I configure through the Avalon-MM are not set correctly or that the registers for the PHY are not set correctly through the MDIO interface. I can not simulate my whole design due to encrypted files. However I can use the generated testbench from Intel and simulate the register values that I a want to set in the MAC

The reference design from Intel uses tcl scripts to configure the TSE module through a JTAG interface. But the register settings don't match with the registers from the datasheet of the TSE. So my question is:

is there a mapping between the JTAG interface and the TSE IP for setting the registers? how could I use the register settings from the tcl script in my vhdl design?

I am using the MAX 10 development kit with Dual Ethernet port and 2 PHY’s.

[Deshi_Intel]

Hi Mdehp,

Intel FPGA TSE reference design has additional wrapper design on top of TSE IP hence the register offset will be difference.

You should follow by the register mapping in below TSE IP user guide if you are using your own TSE design.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Thanks.

Regards,

dlim