Hai,I am using Qsys to integrate all the custom IPs developed.I am using NiosII SBT to access the IPs. When i add a new IP to Qsys and try to access from Nios,its not working.Does anyone have these kind of probs? By adding a custom IP ,the nios ii goes to the reset state.who is actually resetting the nios?? I have seen that my IPs timing simulation works fine. Please help in this.
I do not know what your Qsys condition.but those are my guess. - who is resetting the nios. it must be you. did you make sure reset pin of Qsys input. if you leave it open which means it is resetting because Qsys reset pin is active low. - Custom IP is not working. how do you check Custom IP? I think you can not check Custom IP as long as Qsys is being reset.
Hai all,Thanks for your replies.I have removed the custom IPs and started building the Qsys with only PIO's. Now I have added upto 45 no: of PIO's in the Qsys and generated the system.After that i have build the quartus project with the generated Qsys. Then i used Nios SBT for debugging.During the debug for the helloworld.c program itself it get resetted.What can be the reason for the reset? I have ensured in the hardware that the pin which is assigned as the reset pin of the nios is active high .Is there any limitation in the no: of PIO's which can be used in a Qsys? I am using Cyclone IV EP4CE22E22I7 FPGA based digital controller card for the development.If i reduce the no: of PIO's it is working fine. Please see the attached Qsys image also. Need help in sorting this issue....
hello manjurgl.do you think reset is active high? normally reset pin of NiosII ( I mean Qsys ) is active low. if you insist it is active high, that is fine. could you upload your Qsys file on this page? I think I can help you.
all right manjurgl.I have generated your Qsys file. can you see attached file one ( image_reset_pin_negative.jpg) the pin's name is "reset_reset_n". this suffix "_n" means negative logic. it is active low. so you have to connect this pin with VCC or reset signal which always high except it is reset. also I have one more advice. the pll has three conduit signals. as Qsys warns you, you should export those signal. especially areset_conduit. you have to export areset_conduit and connect it to GND. when you simulate this module, it will occur problem. did those help you?
hai akira,I have exported areset and connected it to GND,also the reset_n pin is connected to VCC. But still i have the problem of reset.At times it work perfectly ,but at some other time,it won't work and get stuck up . What can be the reason for this? I have checked for any timing violation and there is none.Please help in this.
I am not sure exactly what is going on your system.but one thing I guess is that try giving reset_n signal to your CPU. if your board has a button or something, connect it to reset_n instead of VCC. and reset it before you download NiosII software.
--- Quote Start --- this is a custom made development board for Cyclone IV series. --- Quote End --- You may want to consider getting a sanity check on your Quartus/Qsys/NIOS projects using a commercial board. On your custom board, you need to check all of the usual things whenever you build a new board (power, clock, etc.) Your symptom sounds a lot like the FPGA itself is resetting or reconfiguring, possibly a board/design defect.
Sir,I have check the power level and the clock .That seems to be ok. Also with normal schematic file quartus project i am able to run the program in FPGA.But when i try to use the Nios,then only i am getting all these probs. If i am using the PIO's as output only.Then i am able to work with the project.But if i configure them as bidirectional and set its direction as output,then only its creating the problem.
Try single stepping through your software and watch relevant pins/PIO's in SignalTap to isolate your issue. For example, configure SignalTap to watch all your resets, all your PIO's and their Avalon-MM ports to watch the NIOS write something to them and cause the reset to occur.