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Cyclone 10 DDR3 Address Pin assignment

ACamp22
Beginner
164 Views

Hello,

we have a design with a Cyclone 10 GX, we are using a hard DDR3 controller.

After an early pin placement, the PCB guys asked us to swap some pins (ddr_dq data, ddr_dm and ddr_a).

no problem with ddr_dq data and dm, but when i tried to swap some address pin the fitter raises an error saying something like:

Error(13135): Address/command pin (ddr3_a[0]) is constrained to an illegal location (PIN_B19). The legal location for this pin is PIN_A19

when i set again the pin to A19 the compiler runs without any error

i cant understand why Quartus is complaining about that, maybe this is still written in some file, i searched all the files in the project folder but without success. 

All went fine with ddr_dq and ddr_dm changes

Any idea of why this is happening?

Andrea

 

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1 Reply
sstrell
Honored Contributor II
155 Views

For the hard memory controllers in Cyclone 10 GX, control signal locations (including address) are fixed in their designated I/O bank.  They are not swappable.  DQS and DM pins have limited swappability within their I/O lanes, so you may have gotten lucky there.

You can look at the "Read Me" for the IP to see the suggested placement and if there is anything you can swap.  It is located in:

<project_directory>/<variation_name>/altera_emif_arch_nf_<Quartus_version>/synth/<unique_variation_name>_readme.txt

If you are using the Pro edition of Quartus, you can use the Interface Planner tool to select a legal location for the interface and then perform individual pin swaps.  The tool checks on-the-fly if a swap is legal for the IP and generates a Tcl script you can run which will create all the correct legal pin location assignments.

For more detail on constraining a memory interface design, see this online training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html

 

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