Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
46 Views

Cyclone® 10 GX Avalon®-ST Interface for PCI Express example Simulation

I have followed the recipy as described in "ug_a10_pcie_avst.pdf" , "Intel® Arria® 10 and Intel® Cyclone®
10 GX Avalon®-ST Interface for PCI Express* User Guide", and the configuration seems to have downloaded correctly. However, when I try to simulate in Modelsim, as described in par. 2.4 "simulating the design", by typing "do msim_setup.tcl" (works fine), then "ld_debug", a lot compiles, until the last succesful compile of

# Top level modules:
# DUT_pcie_tb_ip
# End time: 14:29:58 on Jun 26,2020, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 14:29:58 on Jun 26,2020

Then the following error appears:

# vlog -reportprogress 300 -sv ../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_180/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv -L altera_common_sv_packages -work altera_conduit_bfm_180
# ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_180/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 14:29:58 on Jun 26,2020, Elapsed time: 0:00:00


See also line 6119 in the attached transcript file

This module "pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_180_zc3dnuy.sv" does not exist in the directory, however, there is a pcie_example_design_inst_board_pins_bfm_ip.csv file in which reference is made to this module.

Please advice. Regards, Pieter

0 Kudos
3 Replies
Highlighted
Moderator
32 Views

Re:Cyclone® 10 GX Avalon®-ST Interface for PCI Exp...

Hi Sir,

I tried to generate the example design in Quartus pro 18.0 and 20.1, both Quartus also able to generate the file under this path:

\pcie_example_design_tb\ip\pcie_example_design_tb\pcie_example_design_inst_board_pins_bfm_ip\altera_conduit_bfm_180\sim

As a quick hack, may I can upload the file here and see if you can copy it over the path and re-run the simulation.



0 Kudos
Highlighted
Beginner
21 Views

Re: Re:Cyclone® 10 GX Avalon®-ST Interface for PCI Exp...

Hi Tan Boon Chiek,

 

Thanks for providing me the file. After loading, i got an microsoft error 0x80010135, which means something like "Path too long" or "name too long". (which is strange, because <255 characters). Anyway, i shortened the name to something shorter. Then i adapted the corresponding modelsim_files.tcl file.

This did not work. Eventually i had to replace in the 'lappend' command  $QSYS_SIMDIR/.. with the full path name.

I had to do this with several modelsim_files.tcl file. It is really strange, because the files it is calling, are all there, and mostly they are found and compiled, but sometimes not. i give you the modelsim_files.tcl files that I modified. Do you have any idea what could be wrong? It is of course a stupid solution to work with a full file path.

It looks like the simulation works . It is now at 20 usec, and  reported:

# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4429 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17261 ns RP LTSSM State: DETECT.QUIET
# INFO: 17357 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 17409 ns RP LTSSM State: DETECT.QUIET
# INFO: 17473 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 18253 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 20389 ns EP Link Speed change to: Gen1
# INFO: 20429 ns EP Link Speed change to: 0

According the user guide, see Figure 7. Partial Transcript from Successful Endpoint Avalon-ST PIO Simulation Testbench at page 7, only after 60 usec the reporting is finished.....How long should this simulation take in real time?

Do you have a drawing with a block diagram of the various modules in the system setup?  (more detailed than Figure 3 in the ug_dex_a10_pcie_avst_pdf document)

The transcript references to Stratix II, Stratix III, IV and V. Does this matter when mapping this to the Cyclone10GX?

Looking forward to your feedback.

Regards, Pieter

0 Kudos
Highlighted
Moderator

Re:Cyclone® 10 GX Avalon®-ST Interface for PCI Exp...

Hi Pieter,


Perhaps you can try with a newer version of quartus and generate the IP into the short path. Sorry that I have no idea with the .tcl file, and the problem is not able to replicate at my side.

I run the simulation and it is complete less than 15 minutes. Below is the end of the transcript.

It is expected the transcript referring to other device because some of the file is re-use and not change the device name accordingly. Anyway, this should be improve to avoid user confusion. I will channel this back to development team.


# INFO:          77960 ns BAR   Size      Assigned Address Type                                                           

# INFO:          77960 ns ---   ----      ----------------                                                                 

# INFO:          77960 ns BAR1:0 64 KBytes 00000001 00010000 Prefetchable                                                   

# INFO:          77960 ns BAR3:2 256 Bytes 00000001 00000000 Prefetchable                                                   

# INFO:          77960 ns BAR4  Disabled                                                                                    

# INFO:          77960 ns BAR5  Disabled                                                                                     

# INFO:          77960 ns ExpROM Disabled                                                                                    

# INFO:          79104 ns                                                                                                    

# INFO:          79104 ns Completed configuration of Endpoint BARs.                                                          

# INFO:          79920 ns ---------                                                                                          

# INFO:          79920 ns TASK:downstream_loop                                                                               

# INFO:          80720 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          81512 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          82280 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          83048 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          83800 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          84560 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          85328 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          86096 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          86872 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# INFO:          87656 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840                                  

# SUCCESS: Simulation stopped due to successful completion!

# Simulation passed


0 Kudos