Cyclone 10 GX PCIe - problems with memory write TLP packages

[FPGADev]

Hi,

we try to port/evaluate a working Cyclone V PCIe application (running with an ARM) to the the DK-DEV-10CX220-A-Kit (running with an X86-64). The OS is on both platforms Linux (5.x.x) with a custom kernel driver.

We use the PCIe MSI, MBAR and memory write TLP for DMA (FPGA -> CPU).

The MSI and MBAR (read/write) is working fine but we have big problems with the DMA.

We tried 32/64-Bit memory write TLP, different Linux DMA-APIs but the data send from the Cyclone 10 never hit the CPU memory.

Is there any known problem with PCIe Cyclone 10 GX and an X86-64?

Is there a working example for the Cyclone 10 GX?

[SengKok_L_Intel]

Hi,

I'm not aware if there is a similar issue at this moment. If you haven't done so, you may refer to the following link for the Cyclone 10 PCIe AVMM DMA example design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an829.pdf

Regards -SK Lim

[FPGADev]

Hello,

i tried this example but my PC won't start. I think it's a problem with the very big MBAR and i don't have any Bios PCI-Settings suggested in the README. Is there any other example or an example with a "normal" MBAR size?

Regards.

[SengKok_L_Intel]

Alternatively, you can also generate the example design from the PCIe IP GUI, From the design tap, you can select DMA, and then click on generate example design. But with the Internal descriptor controller enabled, the BAR address has to set to 64 bit- prefetchable memory. Besides that, I don't see there is any other example design available.

Regards -SK

[SengKok_L_Intel]

I will set this forum case to close-pending for now. The status will remain in this state for 15 calendar days, simply post a note in this forum and it will be reopened for further investigation.