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Cyclone 10GX PCIe Hard IP bring up

JBayl
Beginner
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Hi,

My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager).  I've programmed it with a basic FPGA code based on example project i've used on the Cyclone 10 dev board.

Any tips on how i can go about debugging this?  I can see refclk activity and perst at logic high.  But the core clock out of the PCIe hard IP is not toggling.  Stuck at logic low.

 

Thanks.

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SengKok_L_Intel
Moderator
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From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



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27 Replies
JBayl
Beginner
639 Views

Hi SK,

Found a hardware fault wherein the translator chip for PERST was populated wrong (rotated 180 degrees).  Fixed it on 1 board and tried the sof and stp files you've sent.  Waveforms attached. 

I can see serdes_pll_locked and io pll locked asserted on both sofs.   Board is still not detected by windows.

Thanks!

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SengKok_L_Intel
Moderator
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The coreclkou and the fpll counter are still zero. Does the clk0 (27Mhz) change to 54Mhz is expected?


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JBayl
Beginner
629 Views

Hi SK,

That's weird, clk0 at pin U1 is fixed at 27Mhz from an output of CDCEL913PWR.  This CDCEL913PWR isn't programmed and just passes through its input clock of 27Mhz.  Scope shows constant 27Mhz output.

I've done a couple of SignalTap runs and the values are changing for clk0_freq.  Most of the time in multiples, like 27Mhz,  54Mhz, and 108Mhz.  Sometimes odd values like 81Mhz.  That's with top_cal.sof.

Thanks!

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SengKok_L_Intel
Moderator
2,788 Views

From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



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JBayl
Beginner
605 Views

Thanks SK!  Your responses helped a lot in narrowing down the issue.

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SengKok_L_Intel
Moderator
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If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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GRose12
Beginner
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Hi,

I have a new design using the Cyclone 10GX 10CX105YF672 part. I am trying to get my PCIe Hard IP running. I am concerned that I may have connected to the wrong transceiver pins. I am creating a Gen2 1X PCIe interface. I connected the PCIE-TX to U26/U25 pins and I connect the PCIE-RX T23/T24. I connected the PCIE_REFCLK to U22/U21. I am not able to see the clock in signal tap coming out the coreclkout_hip signal at all. I'm concerned that I should have used a different clock pair of pins (pins N22/N21). 

 

If I am right that I am on the wrong clock pins, is there a way to share clock pins within the PCIe Hard IP Tool?

 

Thanks

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