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JBayl
Beginner
142 Views

Cyclone 10GX PCIe Hard IP bring up

Hi,

My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager).  I've programmed it with a basic FPGA code based on example project i've used on the Cyclone 10 dev board.

Any tips on how i can go about debugging this?  I can see refclk activity and perst at logic high.  But the core clock out of the PCIe hard IP is not toggling.  Stuck at logic low.

 

Thanks.

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13 Replies
SengKok_L_Intel
Moderator
133 Views

Hi,


What is the target speed of PCIe, is this Gen2x4?


What is the status of the following signals?

  1. ltssmstate
  2. current_spped
  3. lane_act


Regards -SK


JBayl
Beginner
112 Views

Hi SK,

Its set to Gen2x1 64 bit, 125Mhz.

I found references to the signals you mentioned in Section 15.2 from here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

I'll update you once I've managed to get Signal Tap setup.

Thanks!

 r/jb

 

JBayl
Beginner
82 Views

Hi,

I'm having issues using Signal Tap.   In stand alone set up using custom test jig providing 3.3V power to the PCIe board, FPGA programming works, that's using either Programmer or Signal Tap.  I can also program the quad serial config device (Micron's MT25QU256) through Programmer.

But Signal Tap reports that I still need to Program the device to continue even after successful SOF programming.

When the PCIe board is inside a PC, Signal Tap can't program the FPGA.  It reports that CONF_DONE pin failed to go high on device 1.  There's only 1 FPGA device on the chain.  

Its looking like a hardware issue because 2 boards have the same behaviour, but the fact that Programmer works and Signal Tap doesn't confuses me a bit on where to look.  Any advice?

Just in case, the FPGA is a 10CX085YU484I5G.  Saw some posts pointing to Stratix device issues.

Thanks!

SengKok_L_Intel
Moderator
53 Views

Hi,


Could you please ensure you have saved the signal tap properly, and then enable it from the Assignments (Quartus Menu)-> Settings -> Signal Tap Logic Analyser -> Enable Signal Tap logic analyzer (with the correct file name) before compiling the design?


JBayl
Beginner
45 Views

Hi SK,

Signal Tap is now running OK.  I created the STP file based on Section 15.4 on ug_01145_avmm (2019.12.20) Intel Arria/Cyclone MM Interface for PCIe User Guide.  Most of the automatically added signals are red, so I searched for the nodes and re-added a few key signals.

I don't see any activity on the ltssmstate, currentspeed, or lane_act.  PERST also appears to be stuck HIGH.  I use PERST as a trigger when it transitions to ZERO, or when it has a zero value on Signal Tap.

Here are my steps:

1. power on PC with PCIe card inserted that's hooked up on a byteblaster on a different machine.

2. program the FPGA using Programmer (SOF).

3. Run Analysis on Signal Tap.

4. Initiate a Restart on the PC (through Windows, not Reset button) )with the PCIe card.  I'm assuming a reenumeration happens here. I can see PERST toggling when I do this PC restart  but Signal Tap isn't capturing it.  I've inserted a counter, and Signal Tap triggers on it when I set the trigger to a counter value.

cause core_clk_out_clk looks stuck.  What would cause this if refclk is toggling and the system isn't in reset? 

Power up sequence looks OK.  3.3V first, then 0.9/0.95, then 1.8, then 3V.  All within 100ms with the main 3.3V input from PCIe kicking it off. 

Thanks!

SengKok_L_Intel
Moderator
40 Views

Can you attach a simplified PCIe design that can replicate the problem here? I would like to do a sanity check on your design. Thanks.


JBayl
Beginner
36 Views

Attached. Thanks!

JBayl
Beginner
27 Views

Hi,

I've powered up 3 boards and all aren't getting recognized.  Main issue I see is that the core_clk_out_clk output of the HIP isn't toggling.  I tied it up to a counter to a test point and no activity.  PERST is high, which is OK, deasserted state.  Refclk is toggling OK.

I think that may be the reason why I can't see the ltssmstate and other debug signals not toggling.  No clock.  Any advice where I should look?

Power up sequence looks OK.  All sources OK within 100ms. 

Thanks!

SengKok_L_Intel
Moderator
16 Views

Hi, 

Could you please use the attached SOF file and capture the signal tap? I would like to see if I can spot anything.

JBayl
Beginner
12 Views

It's getting triggered right away.   See attached pdf with screen shots. 

Result is the same with opening the stp file and programmer independently or adding the STP on a project, compile, and then Signal Tap programs the FPGA with the SOF you've provided.  freq_out is the only signal changing.

Noticed that the serdes_pll_locked and pll_locked_fpll isn't high.  I assume these are high asserted.  May explain why i'm not seeing coreclkout.  But what's causing it...??? 

JBayl
Beginner
9 Views

Power supply sequencing looks correct with about 21.6ms elapsed from when 3.3V (PCIe power input) is OK up to the last power group's Power OK (3rd) asserts.

Conf_Done asserts 415ms after 3.3V is OK.

SengKok_L_Intel
Moderator
4 Views

Is the clk0 in your design a free-running clock? What is the frequency? Does the PCIe ref clock is from the RP (via gold finger), or it is a local clock?


JBayl
Beginner
2 Views

clk0 @ pin U1 is a 27Mhz free running clock.  This clock is meant for our custom logic.

PCIe refclk is from PC through the gold fingers.  I have it at 100Mhz.