My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example project i've used on the Cyclone 10 dev board.
Any tips on how i can go about debugging this? I can see refclk activity and perst at logic high. But the core clock out of the PCIe hard IP is not toggling. Stuck at logic low.
From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.
Its set to Gen2x1 64 bit, 125Mhz.
I found references to the signals you mentioned in Section 15.2 from here:
I'll update you once I've managed to get Signal Tap setup.
I'm having issues using Signal Tap. In stand alone set up using custom test jig providing 3.3V power to the PCIe board, FPGA programming works, that's using either Programmer or Signal Tap. I can also program the through Programmer.MT25QU256)
But Signal Tap reports that I still need to Program the device to continue even after successful SOF programming.
When the PCIe board is inside a PC, Signal Tap can't program the FPGA. It reports that CONF_DONE pin failed to go high on device 1. There's only 1 FPGA device on the chain.
Its looking like a hardware issue because 2 boards have the same behaviour, but the fact that Programmer works and Signal Tap doesn't confuses me a bit on where to look. Any advice?
Just in case, the FPGA is a 10CX085YU484I5G. Saw some posts pointing to Stratix device issues.
Could you please ensure you have saved the signal tap properly, and then enable it from the Assignments (Quartus Menu)-> Settings -> Signal Tap Logic Analyser -> Enable Signal Tap logic analyzer (with the correct file name) before compiling the design?
I've powered up 3 boards and all aren't getting recognized. Main issue I see is that the core_clk_out_clk output of the HIP isn't toggling. I tied it up to a counter to a test point and no activity. PERST is high, which is OK, deasserted state. Refclk is toggling OK.
I think that may be the reason why I can't see the ltssmstate and other debug signals not toggling. No clock. Any advice where I should look?
Power up sequence looks OK. All sources OK within 100ms.
It's getting triggered right away. See attached pdf with screen shots.
Result is the same with opening the stp file and programmer independently or adding the STP on a project, compile, and then Signal Tap programs the FPGA with the SOF you've provided. freq_out is the only signal changing.
Noticed that the serdes_pll_locked and pll_locked_fpll isn't high. I assume these are high asserted. May explain why i'm not seeing coreclkout. But what's causing it...???
Is the clk0 in your design a free-running clock? What is the frequency? Does the PCIe ref clock is from the RP (via gold finger), or it is a local clock?
Could you please add the following in the QSF file, and then recompile the design and capture the signal tap again?
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1
Attached pdf shows what i'm seeing on signal tap.
Added that line you suggested on qsf, recompiled, programmed the MT25QU256, then power cycle.
Run acquire on SignalTap. I used clk0 (27Mhz) free running clock as SignalTap clock source.
Rechecked pin connection guidelines and all looks OK. It all appears to be pointing to PLL not locking...
Could you please also check the CLKUSR, to ensure it is properly connected with the correct clock frequency and the clock is stable at the start of the device?
clkusr is sourced from a XG-1000CA 100.0000M-EBL3 powered @1.8V (group2 power supply) with output frequency of 100Mhz hooked up on pin AA6 (10CXYU484). It looks clean and OK at power up on a freshly powered board.
But not on a board that's been powered up too long. Can feel the board hot with 1.8V getting periodically shutdown by regulator.
I'm using EN6340QI for 0.9 and VCCT/R_GXB. EN5319QI for 3V and 1.8V.
See attached pdf.
Configured the FPGA. Acquired and got the signals as in the pdf.
Restarted the PC and tried acquisition multiple times and same output waveform with freq_out the only signal changing.
The power on sequence of the regulators looks OK and within 100ms. What else could I still be missing...