Hi,I am connecting two 16-bit DDR2 devices (32-bits total) to an EP3C55F484. I am connecting the devices to the bottom banks (bank 3 and 4). The Cyclone III databook states that the CK/CK# pins cannot be placed on the same row or column as the DQ pins. I am not sure I understand what this means. I have constrained the four DQS and DM pins, but I have left all other pins for Quartus to assign. Looking at the post-fit pin placements, the CK and CK# pins are placed on T10 and T11. But in both the columns 10 and 11, and the row T there are DQ pins. I have tried to assign the pins to locations so that there are no DQ pins in the column, but then I get several lengthy warning about the placement of the CK pin. Can anyone shed some light on how to interpret this requirement? Regards, Niki
I have never used DDR2 memory with a Cyclone III so I am not sure exactly what the requirements are. However, while working with other IP I have learned that when the documents are referring to row or column I/O, it is not referring to the rows and columns of the BGA pin matrix, but the internal layout of the actual chip die.To aid in placing pins which have special requirements like this, I find it is easier to open the "Pad View" in the Pin Planner. When you click a pin in either view, the pin will also be highlighted in the opposite view. The pins along the top and bottom are the row I/Os, and the pins to the left and right are the column I/Os.
Hi Kevin,Thanks! After sending the message I realized that row/column could not refer to BGA pins since not all packages are BGA! So I guessed it had to do with the die, but I would not have figured it without your pointer. Looking at the Pad View, I see my CK/CK# clock pair in a group of three pins, where the third pin seems to be unused in my package (probably used in the larger BGA). I guess then that the requirement means that none of the other pins in a group containing the CK/CK# pins are allowed to be DQ pins? Regards, Niki