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Cyclone V (5CGXFC7D7F31C8) DDR2 SODIMM UniPHY Controller, example project compilation

Altera_Forum
Honored Contributor II
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Hi! 

 

I generated controller (DDR2 UniPHY) for Micron DDR2 MT16HTF51264HZ 4GB SO-DIMM module. The FPGA is Cyclone V 5CGXFC7D7F27C8. Right now I try to compile example_project that was generated together with the IP megafunction. After I run Synthesis&Analysis and then run *.tcl script for pin assignments compilation of the whole project is successful. 

 

But then I want to assign pins and check if my assignments are correct. I know that DQ, DM, and DQS pins have to be connected to the DQDQS groups. I connect the whole memory interface to the bottom of the device. In documentation I found information that on the bottom there are 10 DQDQS groups. So I connect DQ[7..0], DM[0], DQS[0] to the first group and so on. 

 

When then I try to compile the example_project with my pins assigned I got an error: "Error (175001): Could not place global clock driver ddr2_ctrl_example_if0:if0|ddr2_ctrl_example_if0_pll0:pll0|pll_afi_clk~CLKENA0" 

 

Can You tell what do I do wrong? Do I miss something? Is it possible to compile the whole design without any pins assigned and then back-annotate the device to see which pins are suggested by fitter to be used? 

 

Regards!
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