Re: Cyclone V - DDR3 UniPHY memory controller example design synthesis error

Altera_Forum · ‎04-10-2012

Hi folks,

I was trying to add a DDR3 UniPHY memory controller example design into an existing project, but I always get the same error message when I run analysis & synthesis:

error (17044): illegal connection found on i/o input buffer primitive ddr3_ctrl_example:ddr3_ctrl1|ddr3_ctrl_example_if0:if0|ddr3_ctrl_example_if0_p0: p0|ddr3_ctrl_example_if0_p0_memphy:umemphy|ddr3_ctrl_example_if0_p0_new_io_pads:uio_pads|ddr3_ctrl_example_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_cyclonev:altdq_dqs2_inst|strobe_in. source io ddr3_ctrl_example:ddr3_ctrl1|ddr3_ctrl_example_if0:if0|ddr3_ctrl_example_if0_p0: p0|ddr3_ctrl_example_if0_p0_memphy:umemphy|ddr3_ctrl_example_if0_p0_new_io_pads:uio_pads|ddr3_ctrl_example_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_cyclonev:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer.

So in order to eliminate the possibility of having the existing project messing around with the example design, here is what I did:

1. created an empty project

2. instantiated the DDR3 example design I/O pins in the wrapper module named top

3. created a DDR3 memory controller with the example design named: ddr3_ctrl

4. added the ddr3_ctrl_example.qip file into the project, and instantiate the ddr3_ctrl_example module

5. run analysis & synthesis

and I got the same error again:

error (17044): illegal connection found on i/o input buffer primitive ddr3_ctrl_example:ddr3_ctrl1|ddr3_ctrl_example_if0:if0|ddr3_ctrl_example_if0_p0: p0|ddr3_ctrl_example_if0_p0_memphy:umemphy|ddr3_ctrl_example_if0_p0_new_io_pads:uio_pads|ddr3_ctrl_example_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_cyclonev:altdq_dqs2_inst|strobe_in. source io ddr3_ctrl_example:ddr3_ctrl1|ddr3_ctrl_example_if0:if0|ddr3_ctrl_example_if0_p0: p0|ddr3_ctrl_example_if0_p0_memphy:umemphy|ddr3_ctrl_example_if0_p0_new_io_pads:uio_pads|ddr3_ctrl_example_if0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_cyclonev:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer.

However, if I open up the example design project file generated by the megawizard, it can be synthesized without a problem. I don't understand why wrapping it with another module would cause an error like this? and where should i look at to fix it? Really lost!

Any idea? am I missing something here?

I really appreciate it :)

Here is what my top level module looks like:module top

(

input pll_ref_clk,

input global_reset_n,

input soft_reset_n,

output [1:0] fpga_ddr3_t_odt,

inout [3:0] fpga_ddr3_t_dqs,

inout [3:0] fpga_ddr3_t_dqs_n,

inout [31:0] fpga_ddr3_t_dq,

output [3:0] fpga_ddr3_t_dm,

output fpga_ddr3_t_clk,

output [1:0] fpga_ddr3_t_cke,

output [2:0] fpga_ddr3_t_ba,

output [15:0] fpga_ddr3_t_a,

output fpga_ddr3_t_we_n,

output fpga_ddr3_t_rst_n,

output fpga_ddr3_t_ras_n,

output [1:0] fpga_ddr3_t_cs_n,

output fpga_ddr3_t_clk_n,

output fpga_ddr3_t_cas_n,

input oct_rzqin,

output local_init_done,

output local_cal_success,

output local_cal_fail,

output drv_status_pass,

output drv_status_fail,

output drv_status_test_complete

);

ddr3_ctrl_example ddr3_ctrl1(

.pll_ref_clk (pll_ref_clk),

.global_reset_n (global_reset_n),

.soft_reset_n (soft_reset_n),

.mem_a (fpga_ddr3_t_a[13:0]),

.mem_ba (fpga_ddr3_t_ba),

.mem_ck (fpga_ddr3_t_clk),

.mem_ck_n (fpga_ddr3_t_clk_n),

.mem_cke (fpga_ddr3_t_cke[0]),

.mem_cs_n (fpga_ddr3_t_cs_n[0]),

.mem_dm (fpga_ddr3_t_dm),

.mem_ras_n (fpga_ddr3_t_ras_n),

.mem_cas_n (fpga_ddr3_t_cas_n),

.mem_we_n (fpga_ddr3_t_we_n),

.mem_reset_n (fpga_ddr3_t_rst_n),

.mem_dq (fpga_ddr3_t_dq),

.mem_dqs (fpga_ddr3_t_dqs),

.mem_dqs_n (fpga_ddr3_t_dqs_n),

.mem_odt (fpga_ddr3_t_odt[0]),

.oct_rzqin (oct_rzqin),

.local_init_done (local_init_done),

.local_cal_success (local_cal_success),

.local_cal_fail (local_cal_fail),

.drv_status_pass (drv_status_pass),

.drv_status_fail (drv_status_fail),

.drv_status_test_complete (drv_status_test_complete)

);

endmodule

Altera_Forum · ‎05-17-2012

I have reported this problem to the "Altera Service Request online" without no feedback for a month!

"error (17044): illegal connection found on i/o input buffer primitive ...

also drives out to other destination than the buffer."

Maybe you can try the altmemphy IP core in your project!

Altera_Forum · ‎05-17-2012

Did you run the tcl scripts generated by the memory compiler?