Showing results for 
Search instead for 
Did you mean: 
Honored Contributor I

Cyclone V GX PCIE Hard IP DMA problems

I used Cyclone V GX PCIE Hard IP with Avalon-ST interface, I don't use Qsys to generate the PCIE core, but use the IP catalog in the project. 

Now I can receive the correct memory read data from PC, and send the correct data to PC by cpID TLP. 

But the PC can not receive any data when I send by the DMA with either 3 header aligned TLP nor 4 header aligned TLP. 

I have used the logic analyer to capture the DMA address which the PC send, and the address I send to PC in DMA is correct. 


Does it need to enable some signal to open DMA function or need to adjust some signal before starting DMA? 


Please send me a example of DMA tx of Cyclone V GX PCIE Hard IP with Avalon-ST interface but without Qsys. 


Thanks very much!!!
0 Kudos
0 Replies