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Cyclone V - LPDDR2 problems - Guaranteed read failure


This is an implementation on a bespoke board that compiles/synthesises but fails calibration as indicated by Signal Tap.

I have implemented the External Memory Interface Toolkit and really all that seems to tell me is the IP has failed immediately on

  1: Read Calibration - Guaranteed read failure

I have scoped most[1] of the signals between the FPGA and SDRAM and they all toggle during reset or a calibration. ([1] There are DQs that are non-trivial to get to.)

The board has had the memory changed and is not something I want to do again.  The pinouts have been checked and rechecked.

The memory I am using is an ISSI device which should be JEDEC compatible and I have checked has the same set of Mode Registers as a Micron device.

Apart from writing my own diagnostic module to check things like operation of mode register etc, I feel utterly stuck.

The IP has a minimum speed of 166MHz which is a shame as the memory can run down to 10MHz.

Can anyone enlighten me to anything I can do to understand the failure and move forward?


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I do not know if this helps ,but there is  Hardware Debugging Guidelines in the document if you need additional debugging items.

starting page 565