Cyclone V SX - dual 10Gbe XAUI

[BAbbott]

Hi,

I'm looking into implementing a dual XAUI interface for 10Gbe ethernet using the XAUI IP in a Cylcone V SX (5CSXFC5). I've been able to implement one, but I'm having issues implementing two. Theoritically, is it possible to implement two using the 9 GXB transceivers (Lanes 0-3 and Lanes 5-8) or do I need to go a different route?

It also looks as though 10Gbe is the only option - should I be using the 156Mhz reference clock for the REFCLK pins for this implementation or can they run to global clock input pins?

[SengKok_L_Intel]

Please refer to Figure 4-23 in the following link, each XAUI link requires a dedicated CMU PLL, and it will occupy either CH1 or CH4, therefore, 9 XCVR channels device is not enough to have two XAUI interfaces.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v3.pdf

Regards -SK

[SengKok_L_Intel]

Besides, you have to use the 156.25Mhz as the input reference clock frequency for the XAUI.

[BAbbott]

So using CH4 for the input PLL + CH5-8 as the interface should be sufficient with REF_CLK0 being the input for the 156.25MHz?

Making sure I understand that correctly.

[SengKok_L_Intel]

Hi,

This is suggested to compile with a simple design to see if the Quartus allow this kind of combination to fit and whether there is any critical warning.

[SengKok_L_Intel]

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.