I'm looking into implementing a dual XAUI interface for 10Gbe ethernet using the XAUI IP in a Cylcone V SX (5CSXFC5). I've been able to implement one, but I'm having issues implementing two. Theoritically, is it possible to implement two using the 9 GXB transceivers (Lanes 0-3 and Lanes 5-8) or do I need to go a different route?
It also looks as though 10Gbe is the only option - should I be using the 156Mhz reference clock for the REFCLK pins for this implementation or can they run to global clock input pins?
Please refer to Figure 4-23 in the following link, each XAUI link requires a dedicated CMU PLL, and it will occupy either CH1 or CH4, therefore, 9 XCVR channels device is not enough to have two XAUI interfaces.
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