HelloIn my design i am using Frame buffer that buffer video data in SDRAM and a Clocked video output IP in SOPC I need to integrate a DMA (direct memory access ) in my design between the frame buffer and the Clocked video output . If it's possible , how the connections should be made . Thank's for any further help .
Can you explain the question more?The Frame Buffer takes the incoming data, buffers it and gives you an output, wich can be assigned to the CVO. You just connect the two and configure them accordingly your Input/Output. They are connected via Avalon-Bus then. (if you mean the FrameBuffer from VIP-Suite) What do you want to do?
The frame buffer use an external SDRAM to buffer video packets and then assign them to CVO as you saidMy question is that i need to add a DMA (direct memory access) to that system to manage data . How could that be done ? Thank's for your help
OK, now it is clearer. I would not try to implement that on my own, because Altera provides components for that. (except you really have to implement it yourself for some case)You can add some type of SDRAM-Controller. I normally take the easy controller instead of the highspeed one, because it is easier to configure. The highspeed controller needs clockbridge and pll, because you have to alter the phase of the clock according to your designs speed. So take a look at the SOPC-System I attached, I would design an easy output system to CVO like that. The configuration you must find out from the documentation of your dev-board. In Quartus you then add the pins to the SDRAM. (be aware, that dq is a bidir pin) Good Luck.
If it is really a controller you have written yourself, then the easiest way in my opinion is to implement the avalon-bus to it. The interface is quite easy to handle if you look into some example code. Search here in the forum like: http://www.alteraforum.com/forum/showthread.php?t=19053 You can then Import the HDL-File into the SOPC Wizard, wich creates you the needed .tcl File that inherits the interface description for the sopc. I think you could write that also by hand, but have not tried as the wizard worked fine here.There are also hints in the forum. Try to search a bit. The idea to implement own code or connect external hardware to the nios is quite wide spread and is discussed here quite often before. Perhaps search for "Avalon" to get more information about implementing the bus and go get Alteras interface description. So far from me, good luck! (Edit: perhaps I am missing your question again. Try to describe more in detail then once again.)
Ok, then I got it wrong. I haven't worked with that component so far. I assume you have looked into the documentation from altera. So I can't help you with that.Have a nice weekend! Good luck!
I have seen, that you have made a new thread. So I thought about your project again and find, that I don't undestand, why you want to use the DMAController for accessing the SDRAM. When the FrameBuffer is using the RAM for Buffering the VideoData the SDRAM-Controller normally works fine. I am just curious, what do you want to achieve by using the DMA-Controller?Thanks.
What i need is a fast manipulations between the Sdram and the clocked video output . I need to bypass the nios in controlling the write and the read .Sorry but i am new in FPGA design , and i am working on an university project.
Hm? That does not explain it in detail anyway what you are planning to do, but perhaps it might be better for you to read from the SDRAM directly like with the FrameReader Altera provides. That one can generate you the Frame around the pixeldata the CVO needs to output an image and then you might build a module in VHDL that implements your write access.From the SDRAm you cannot normally get the data out to the CVO directly I think. It could be that the FrameBuffer also throws away the datapacket around the incoming data and generates a new one when it reads. I try something quite similar, to write a frame directly into sdram and read it from there again to output to the DVI-Monitor and my result is to implement an module, that takes the CVI-data via Avalon-ST, throws away the sof, eof. Writes the pixeldata at a specified address into sdram and on the other side the Framereader from Altera reads the SDRAM continuously where the whole frame is stored and outputs it to the CVO with the sourrounding data. That works quite well when you are using the SDRAM-Controller, because otherwise you will have to manage the accesses from the writer and reader to the sdram with some extra logic. I implemented for the writing to sdram an Avalon-MM interface into my written module, Input is Avalon-ST and you can also implement easily an CSR-Interface to manipulate something while at runtime. It is just my two cent, but perhaps that gives you another idea. I don't know if this matches what you do in any kind, but I just wanted to tell it anyway ;-) Have a nice weekend and good luck with your university project, Peet.
hi,peet_2maybe,I can answer your questions!~ now,I want to acquire video data and output them though ethernet IP "TSE_MAC"(tripple speed ethernet),now I have realize test data saved in sdram trasmitted to TSE_MAC by sgdma ,then to PC. now,I want to make video data which saved in sdram instead of test data ,so maybe I want to inset a sgdma after framebuffer but not connect to clocked video output. is that way reasonable to reach my goal? best regards~!
Hello peet 2.Now,I have a similar question.I use a buffer with RAM to buffer vidio data and I want to use DMA to transfer the data in the buffer to SDRAM. I know the avalon MM interface is needed, also I already know how to design the avalon MM interface. But, I don't know how to relate the DMA with the avalon MM interface. The question bother me so long ,can you help me,thanks very much!