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Altera_Forum
Honored Contributor I
1,935 Views

DCFIFO Megafunction simulation problem

Hi,  

 

I am attempting to use DCFIFO megafunction in my design, but i can't get it running!!  

 

The input data to be written to FIFO is (45 bit parallel) streaming video data clocked at 5MHz (wrclk). Data at output of the FIFO is read at 100MHz clock(rdclk); to be used in rest of the design.  

 

I've taken out rdempty control signal only as rdclk>>wrclk and there is no probability of getting FIFO full.  

 

At input of FIFO, data is updated on every posedge of wrclk so, i've hardwired wrreq signal to logic 1 (I require FIFO to assume valid data at input on every rising edge of wrclk). rdreq signal depends on rdempty signal i.e. rdreq = ~rdempty; 

 

I am not using aclr signal as I've hardwired wrreq to logic 1(As scfifo and dcfifo megafunction user guide says: Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high.). 

 

Overflow and underflow protections are enabled and I am using FIFO in normal mode...  

 

To isolate the problem, i have tried functional simulation (Altera Modelsim) of DCFIFO only. In the test-bench i've hooked input data port to a certain value, wrreq to logic 1, rdreq = ~rdempty. Nothing is coming out of FIFO, simulator shows q(data out) and rdempty ports in high impedance (z) state.  

 

What am i doing wrong here and how do i get it running?  

 

Also, can DCFIFO effectively bridge this much difference in clock domains i.e. 5MHz:100MHz? 

 

regards, 

Ihtesham
0 Kudos
10 Replies
Altera_Forum
Honored Contributor I
109 Views

The big difference between the two clocks shouldn't be a problem. 

Are you sure those signals are in high impedance state? I don't see how the model could produce this. If there were an initialization problem they would rather be in the U or X state, but not Z. 

Are you sure the FIFO is connected correctly in your testbench?
Altera_Forum
Honored Contributor I
109 Views

Could it be because you are reading empty fifo?

Altera_Forum
Honored Contributor I
109 Views

i've the attached the waveform and here the test-bench code 

 

`timescale 1ps/1ps module tb_dc_fifo(); reg wr_clk, rst, rd_clk; reg data; reg rdreq, wrreq; wire q, data_out; wire rdempty, rdreq_o; initial begin wr_clk = 1'b0; rd_clk = 1'b0; data =45'h0AAAAAAAAAAA; rst = 1'b1;# 45 rst = 1'b0; rdreq = 1'b0; wrreq = 1'b1; end always# 100 wr_clk = ~wr_clk; always# 5 rd_clk = ~rd_clk; //---------------FIFO INSTANTIATION------------------- fifo_new fifo_new_inst ( .data ( data ), .rdclk ( rd_clk ), .rdreq ( rdreq_o), .wrclk ( wr_clk ), .wrreq ( 1'b1 ), .q ( q ), .rdempty ( rdempty ) ); //-------------READ LOGIC MODULE INSTANTIATION-------- read_control_logic read_control_logic_inst( .rst(rst), .rdclk(rd_clk), .rdempty(rdempty), .rdreq(rdreq_o), .q_read(q), .dataout(data_out) ); endmodule  

 

Any help will be much appreciated!!
Altera_Forum
Honored Contributor I
109 Views

From what I can seen, the FIFO output signals are dangling. 

Is modelsim correctly finding the fifo_new component?
Altera_Forum
Honored Contributor I
109 Views

when i instantiate the DCFIFO core, these file gets created: fifo_new.v, fifo_new_inst.v, fifo_new_bb.v, fifo_new.qip. I have included only the black-box file i.e. fifo_new_bb.v in my modelsim project.  

 

Is there anything wrong here? should i also include fifo_new.v ??
Altera_Forum
Honored Contributor I
109 Views

Yes, you need to compile fifo_new.v instead of fifo_new_bb.v

Altera_Forum
Honored Contributor I
109 Views

ok, i've included fifo_new.v and here comes the error: 

 

# 3 compiles, 0 failed with no errors. vsim work.tb_dc_fifo# vsim work.tb_dc_fifo # Loading work.tb_dc_fifo# Loading work.fifo_new# ** Error: (vsim-3033) E:/ihtesham/Tasks_And_Projects/FPGA/IPCores/fifo_error/fifo_new.v(74): Instantiation of 'dcfifo' failed. The design unit was not found.# Region: /tb_dc_fifo/fifo_new_inst# Searched libraries:# E:\ihtesham\Tasks_And_Projects\FPGA\IPCores\fifo_error\work# Loading work.read_control_logic# Error loading design The design unit was not found!!  

i am using modelsim (A)SE, so all atera libraries should be pre-installed and compiled, but looking at the searched libraries, it doesn't seem to be searching all altera libraries... 

 

# Searched libraries:# E:\ihtesham\Tasks_And_Projects\FPGA\IPCores\fifo_error\work how should i make it search altera_mf library??
Altera_Forum
Honored Contributor I
109 Views

 

--- Quote Start ---  

how should i make it search altera_mf library?? 

--- Quote End ---  

 

Add this to the vsim command:-L altera_mf
Altera_Forum
Honored Contributor I
109 Views

Hi, did you solve the problem? 

 

following is my problem: 

 

when I generated a DCFIFO with read clock different from writing clock, the rdempty signal always keep high, and rdusew signals don't function, too. so I can't read data from FIFO. after checking the wrempty and wrusew signals, they function correctly, so I use wrusew to detect and correctly got the desired. following is my verilog: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14816  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14817  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14818  

 

so my qustions are: 

1. what is wrong with rd signals? 

2. when using the same clock for both rd and wr clock, everything works fine(using either wrempty or wrusew to detect), but when rdclock is different from wrclock, either faster or slower, the data readout is not exactly what it received.
ZLu001
Novice
109 Views

I met the same problem three years ago and used wrusew or wrempty to finish the design. I tried recently, the rdempty problem still there, any solution now?

another problem, I tried to use different clocks for reading and writing, it doesn't function properly. any help?

as for the  altera_mf library, in which file I should add the" -L altera_mf" in?

Thanks a lot.

 

 

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