I have an issue with the Calibration Status, with the ip : "LPDDR2 SDRAM Controller with UniPHY."Version 15.1.
Condition low tempereture (-20°C -4°F):
If I set a MEM_CLK_FREQ = 300.0MHz, sometimes the calibration fails :
=> hmc_DDR_status_local_cal_fail goes high,
=> hmc_DDR_status_local_cal_success goes low.
=> But If I set a MEM_CLK_FREQ = 400MHz, the calibration always seems OK (hundred tests).
I'd like to know, how the increase of MEM_CLK_FREQ will affect the DDR calibration process?
For more complete information about compiler optimizations, see our Optimization Notice.