FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6511 Discussions

DDR DQS BANKS 5/6 MAX10 Conflict

Altera_Forum
Honored Contributor II
1,259 Views

In the MAX10M16 the two banks that support DDR memory are bank 5/6.  

The DQS lines for banks 6 is on pins H11/H12.  

The DQS lines for banks 5 is on pins L15/K15. 

 

If i assign the DQS/DQ on bank 6 (pins H11/H12) 

I get an error that says: 

Error (171082): Can't place node "mem_dqs[0]" in location or region "PIN L15" -- location is not compatible with current location of PIN H11 for the node -- location added due to User Location Constraints and IO standards pin placement 

 

If i assign the DQS/DQ on bank 5 (pins L15/K15) 

I get an error that says: 

Error (171082): Can't place node "mem_dqs[0]" in location or region "PIN H11" -- location is not compatible with current location of PIN L15 for the node -- location added due to User Location Constraints and IO standards pin placement 

 

... so i am stuck. What bank should i put my DQS/DQ pins on?  

 

Is there something i need to do to the DQS pins that are not used?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
494 Views

I don't understand. You're putting DQS on pin L15 and the error you get is about pin H11? And vice versa? 

 

If you haven't already, in the Pin Planner, go to the View menu and enable the DQ/DQS pin view. That way you can guarantee you are using the optimized and correct pins.
0 Kudos
Reply