FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR Timing violations

kwkprd
Beginner
1,374 Views

 

Timing violation in task:- Report DDR timing analyzer  

 

setup hold
   Address/Command (Fast 900mV 0C Model) | 0.18 0.18
  Core (Fast 900mV 0C Model) | 1.391 0.012
  Core Recovery/Removal (Fast 900mV 0C Model) | 1.555 0.197
  DQS Gating (Fast 900mV 0C Model) | 0.147 0.147
  Read Capture (Fast 900mV 0C Model) | -0.019 -0.019
  Write (Fast 900mV 0C Model) | 0.023 0.023
  Write Levelling (Fast 900mV 0C Model) | 0.132 0.132
 *DDR Timing requirements not met.

 

The resolution from intel forum :

Resolution

"To work around this issue, please double check all the board skew settings in the MegaWizard or Qsys GUI to make sure all the parameters comply with the Altera recommended layout guidelines."

 

 i have checked all the board skew and ip settings in the design. 

From tool am not getting any timing closure recommendations & summery is empty. how to solve this issue?

 

Violation i got in analyzer tool:-          -0.193 PCIe_X8_SUB_SYSTEM|emif_1|emif_1|ecc_core|core|ecc|io_hmc_ecc_inst|int_master_wr_data_info[2] 

PCIe_X8_SUB_SYSTEM|mm_interconnect_0|agent_pipeline_002|gen_inst[0].core|data1[102]

 

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10 Replies
sstrell
Honored Contributor III
1,333 Views

What device?  What Quartus version?  What are your settings in the parameter editor?  Way more info needed here.

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kwkprd
Beginner
1,305 Views

Thanks for your Reply

 

I have attached the document for your quick reference. 

 

 

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AdzimZM_Intel
Employee
1,284 Views

Hello,


Can you provide the memory datasheet as well?

What is the memory frequency? Can provide the General tab as well?


Regards,

Adzim


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kwkprd
Beginner
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Thanks for your Reply

 

General tab

kwkprd_0-1681213507234.png

 

datasheet:- MTA72ASS8G72LZ – 64GB

 

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AdzimZM_Intel
Employee
1,248 Views

Hello,


I have replicated the issue at my end and I can see the Read Capture timing violation with your EMIF IP setting.

I may suggest to use faster memory component that compatible with your memory device.

From my end, I have used memory speed bin -3200 parameter setting and running at 1066.667MHz clock frequency.

The timing is clean after running the compilation.

I hope you can get a same result as well.


Regards,

Adzim


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kwkprd
Beginner
1,206 Views

Thanks for your reply

 

I have made changes as suggested.

 

but got different violation

 

kwkprd_0-1681370210051.png

 

 older violation message

 

 

kwkprd_1-1681370620407.png

 

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AdzimZM_Intel
Employee
1,152 Views

Hello,


Are you using an Design Example generated from Quartus? Is there any other IP in the design?


What are the changes that you have made? It is possible that you share the changes again?


Regards,

Adzim


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AdzimZM_Intel
Employee
1,064 Views

Hi,


Is there any feedback in this thread?


Regards,

Adzim


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kwkprd
Beginner
1,037 Views

Hi,

 

 consider your suggestion i will try once again after my design updates. 

 

as per this issue concerned i guess it will work after the updates.

Thanks for supporting.

 

 

 

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AdzimZM_Intel
Employee
935 Views

Hi,


Thank you for the feedback.


I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.


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