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DDR on CIII using altera ddio megafunction

Honored Contributor II



i am designing ip core for onfi nand flash controller. it is following DDR protocol. so i want to use altera ddio megafunction to convert data from single data rate to dual data rate and vice-versa. i have question regarding data latch in ddio. 

i want to generate data on DQ line center align to DQS strobe at the time of write operation and for read operation nand device will give data DQ edge aligned to DQS strobe. 


so how can i use ddio in my design? 


i am using Cyclone III 3c120 device for its testing. 


thanx in advance 



vijay sheladiya
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