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I am getting the violation for the nodes
-0.493 PCIe_X8_SUB_SYSTEM|emif_1|emif_1|ecc_core|core|ecc|internal_master_wr_data_ready PCIe_X8_SUB_SYSTEM|mm_interconnect_0|agent_pipeline_002|gen_inst[0].core|data1[50] PCIe_X8_SUB_SYSTEM|emif_1|emif_1_core_usr_clk PCIe_X8_SUB_SYSTEM|emif_1|emif_1_core_usr_clk 3.752 -0.200 4.067 Slow 900mV 100C Model
I am using LRDIMM. How to resolve this violation
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Hi,
I need additional input from you to debug in this timing issue.
Are you able to share the full timing report here? If you can share a design that can replicate the issue also good.
Are you observing timing violation after adding the PCIE IP into the design?
If using only EMIF example design, do you find any timing issue?
You can run DRC in Timing Analyzer GUI. From there, it will generate a list of rules with recommendation that can help to resolve the timing issue.
Regards,
Adzim
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Hi,
This timing violation is occurred between the EMIF IP block and other block.
Some timing closure techniques can help to resolve the issue.
Can you add pipeline or register to path that has timing violation?
What is the recommendation from DRC report in the Timing Analyzer?
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Hi Sir,
I Checked the DRC it is coming as FMAX has reached its maximum limit. some time i am getting the issue like when i read the DDR. I am getting zero.
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Hi,
Can I see your DDR IP setting? Maybe you can take some snapshots from the IP Parameter Editor.
And also can you let me know which memory device that you used?
Regards,
Adzim
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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