HelloI am designing a board which contains a DDR2 SDRAM memory and a CYCLONE IV device. I looked at the development kit of CYCLONE IV schematics and saw that all the signals from/to the ddr2 have an external parralel 50 ohm termination to vtt(0.9v). I read some of the threads regarding the subject but they are quite ambiguous..I don't have enough space on my board so I would love to get a clear answer to the following questions:
I'm already have a my board with Cyclone IV and DDR2 - it already worked without termination. Micron's article says that you don't need termination resistors if you have length less then 62.5 mm.
hi,I have also a small board with cyclone IV / DDR2. When you say that DDR2 works without termination, is it only for dq/dqs or for all signals² : diff clocks, addresses and command signals ? I also see on cyclone III dev kit that FPGA vref IO (VREFBxNy) are connected to DDR_vref. Is it needed ? thanks.
You have to place termination resistor only for diff clock.FPGA vref IO connect to DDR_VREF ( = 1.8V/2) due to io standard used DDR2. Also you have to read ALtera documents about using DDR more carefully