DDR2 HP Controler -- need some help!

[Altera_Forum]

Hello, 

 I'm trying to use DDR2 HP v8.0 controler. I've a stratix II PCIe dev board with 5 memory chips on it. Total memory is 288 Mo.   I generate DDR2 HP with megawizard, native interface, half rate and build some logic around to control it (generate write_request, read_request, datas, monitoring wdata_request and so on)  I am able to write or read in my memory but only continously! I can't make one write (understand one pulse on write_request with the corresponding datas, burst size, byte enable...) or one read (just one pulse on read_request with the correct address).  But if I let my write request pin high, I can write datas continously (except when ddr controler must make a refresh). Same thing with read operation. Only continous read. I can read back data I have write before.  Then, I make a state machine who generate signals. First, I make one write (during one cycle of clock), and after I make one read at the same address (during one clock too). It don't work.  The only way I find is to make write during 2 or 3 cycles of clock and just after make a read during 2 or 3 cycles of clock. But it don't work all the time...   Can someone could help me and tell me why I can read out data (or write data) correctly only if I do that continously ?? Please, if you need more details about my configuration or my code, tell me!  Thanks in advance.  Fabtrice.

[Altera_Forum]

Are you using DDR2 HP component without SOPC? Anyways, are you taking care of feedback signals from controller like rdata_valid and wdata_req signals? I guess DDR2's latency will come into picture and you will not be able to write or read anything immediately you need to wait for its latency period, I guess you should be able to read/write single data by controlling DDR2 HP component using feedback signals given.

[Altera_Forum]

Yes, I use DDR2 HP without SOPC system (with native interface). 

 For feedback signals, I check them correctly.  Really, I don't understand why I can write and read correctly continously but not with one write (in one clock cycle).  I make this test: - I make one write at address '1' (for example) - I wait wdata_request, I send data to write - I wait a couple of clock cycle (maybe 15 cycles) - Then I try read back address '1' with one read. - I wait local_rdata_ready assert and I latch data on bus local_rdata  But I don't read the same thing I write before...  Thanks for your help Ketan. Unfortunaly, I think it's another thing... Someone have got another idea ? Thanks!

[Altera_Forum]

If I understand right, you are operating the controller with a design of your own. The most likely explanation would be a mísunderstanding of interface signals and timing, to my opinion. Did you try with the test driver before? By modification of the test sequence, you should be able to perform single writes and reads also. 

 I also didn't understand exactly, how you performed the continuous operation. With sequentially incremented addresses? With random data?

[Altera_Forum]

Signal back at chip interface in next cycle????