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DDR2 HP Critical Warning

Altera_Forum
Honored Contributor II
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Hello everybody! 

 

I'm trying to implement the DDR2 high performance controller in an SOPC system on a Stratix III, but when building the design with Quartus I get some Critical Warnings like those: 

 

Info: altmemddr_phy_ddr_timing.sdc: Could not find PLL clocks for inst|the_altmemddr|altmemddr_controller_phy_inst|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[1]. Creating PLL base clocks 

Critical Warning: PLL clock inst|the_altmemddr|altmemddr_controller_phy_inst|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

Warning: altmemddr_phy_ddr_timing.sdc: Failed to find PLL input clock pin driving inst|the_altmemddr|altmemddr_controller_phy_inst|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] 

 

After I successfully created the NIOS design with SOPC Builder I executed the .tcl script that makes the IO standard assignment and also added the .sdc file to the Quartus project. Further I made the fitter setting according to the SOPC Builder notes. 

Then I connected the component to the FPGA ports. The ports for the DDR2 memory were named mem_xxx. 

Finally I created my own .sdc file where I created the clock signal. 

 

I haven't tested the design on my target hardware yet because I'm still waiting for the board (Stratix III DSP Development Kit). 

 

Can anybody please give me a hint what I might have done wrong that causes the warnings above? 

 

 

best regards 

Christoph
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Altera_Forum
Honored Contributor II
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it's me again. 

 

If anybody of you has implemented the DDR2 high performance controller on the "Stratix III 3SL150 Development Board" could you please send me your Quartus setting file (.qsf)? 

I had to make the pin assignments myself (because I'm still waiting for my board and thus haven't got a reference design yet) and am afraid I might have made wrong pin assignments. 

 

best regards 

Christoph
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Altera_Forum
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