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Valued Contributor III
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DDR2 HPC2 Timing Simulation fails

Hello, 

 

i am trying to get the example design for the DDR2 Memory controller (HPC2 with ALTMEMPHY) to work. I have spent already a whole week on this issue, but I cant get it to run. I am using Quartus II 11.0 (tried with 9.1 too) and modelsim se 6.6d. I am trying to implement the design on a Stratix III EP3SL340H1152C2. The behavioural simulation works fine, but when I generate the timing model the simulation fails with timing violations (HOLD HIGH and LOW on stratixiii_ddr_io_reg), even though quartus met all timing constraints. I tried the generic memory model and the micron vendor specific memory model (because it was used in the tutorial). I assigned all pins according to the board i am using (Altera DE3 Board).  

 

I followed the advices in the tutorials and manuals. I executed the tcl script and included the *.sdc files in the project. I adjusted the parameters of the controller as specified in the manuals. It still doesn't want to work and I have no idea how to fix the problem. Please help me with this issue. I am really desperate and frustrated atm. I attached the quartus logfile and an image of the modelsim waveform. If u need anything else, please let me know. Thank you very much in advance. 

 

Best regards, 

Martin 

 

P.S. The project i generated the logfiles with, does not contain the exact pin locations. Can't use the actual project, since it is confidential. I assume the simulation should work anyway.
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Valued Contributor III
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here (http://www.altera.com/literature/hb/external-memory/emi_ddr_ug.pdf#page=11) I read that Timing Simulation is still one of the unsupported features of DDR/DDR2 Controllers with ALTMEMPHY.

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Valued Contributor III
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Hi, 

 

thank your very much for your reply. I was working with Xilinx MPMC before and I didnt expect that Altera wouldnt support timing simulation. The question now is: how can I verify my design? I tried to upload the design to the FPGA and the local_init_done signal was never asserted. I am not 100% sure if I may use this signal, since the manual suggested, that it is only for the native-interface and not for Avalon. But I needed some sort of indicator that the memory controller is ready to accept requests. Nevertheless, in the functional simulation everything was fine, so I tried to find out the error through timing simulation.  

 

The SignalTap logic analyzer is not very well suited for debugging purposes, since I cannot access the memory pins and I can only capture a tiny time window of a few clock cycles. Additionally it has great impact on timing performance. I wasn't able to create a design that met the timing requirements. Therefore this might be the reason, why local_init_done hasn't been asserted. Is there any other way I could simulate the the memory controller with some sort of timing enabled? Thank your very much. 

 

Best regards,  

Martin
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Valued Contributor III
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Do you use an evaluation kit, or is it already a custom design? 

 

For the eval kit, you can be sure that the example design should work as described in the UG. Assure that you don’t skip any step, especially regarding constrains, pinning (mind the TCL scripts) and memory parameter file (XML). You could start with a significantly reduced memory frequency, i.e. 125 MHz for DDR2 and longer CAS latency. 

 

I had some good experience with SignalTap checking that the PLL input clock is there (one should be able to see the oversampled lo-freq clock in the output) and see that reset is applied and released as expected – once a signal is part of the SignalTap pin list, one can quickly change the trigger condition. Next you can monitor the example driver’s I/Os (local_read_req, local_write_req, etc.) and see whether it already started driving the controller and whether it gets stuck at the first write access. 

 

Search for ctl_cal_fail, ctl_cal_success, ctl_cal_warning deeper inside the phy part. Without calibration success, the interface will not boot up properly and will not allow any access to the memory. 

 

Good luck.
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Valued Contributor III
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Hi, 

 

I put up a fresh quartus project with my custom IP cores and complete pin assignments. I added the ctl_cal_success, ctl_cal_fail and ctl_cal_warning to signaltap. Unfortunately the signal ctl_cal_fail is asserted. Quartus met the timing requirements only without signaltap. When I insert SignalTap into the design the timing fails quite miserably. I got a -4ns setup slack for: 

 

seq_oct_oct_delay[0] => acq_trigger_in_reg 

 

This could be the reason why the calibration fails. Would it help, if I use another clock for SignalTap? Right now I use the 100 MHz clock of my PLL. Another problem might be the following warning: 

 

 

--- Quote Start ---  

Critical Warning: No exact pin location assignment(s) for 2 RUP, RDN, or RZQ pins of 2 total RUP, RDN or RZQ pins 

Info: RUP, RDN, or RZQ pin termination_blk0~_rup_pad not assigned to an exact location on the device 

Info: RUP, RDN, or RZQ pin termination_blk0~_rdn_pad not assigned to an exact location on the device 

--- Quote End ---  

Do I need to connect these PINs to the design? There are no ports that I could connect them to. 

 

Another warning I am worried about: 

 

 

--- Quote Start ---  

Critical Warning: Memory clock pin mem_clk[0], mem_clk[1] must be placed on the same edge of the device 

Critical Warning: mem_clk[0] was placed on the right edge of the device 

Critical Warning: mem_clk[1] was placed on the bottom edge of the device 

 

--- Quote End ---  

How can I place the mem_clk on the same edge? The PIN assignments are fixed according to the DE3 manual.  

 

Thank you very much in advance. 

 

Best regards, 

Martin
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Valued Contributor III
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Martin, 

 

I’m not familiar with the DE3 eval board. I am pretty sure their PCB layout allows proper DDR2 memory interfacing, so I wonder why you should see mem_clk pin location warnings. 

 

You have to specify where your termination_blk0~_* signals are located. This is described in the HPC2 user manual. 

 

Next make sure that you properly selected the exact DIMM parameters in the MegaWizard. Choose low speed and low CAS latencies at first. Make sure you use the exact pin locations and don’t leave the placement optional for Quartus. 

 

When assigning signals in SignalTap, make sure you keep their number as low as possible as well as the number of samples – but don’t hesitate to raise their numbers when you have to. Don’t enable trigger functionality for signals you don’t intend to use as triggers. It’s all described in the user manual. You might want to go for a half-speed controller or half-speed interface bridge as well, to cut down timing issues. 

 

Start at the lowest possible DDR DRAM clock frequency – typically 125 MHz – and only raise it to the max when you succeeded. 

 

Ah, and leave out all your custom stuff for the moment. Best is to start a new project with just the DDR2 HPC2 demo app (example_top) and nothing more. Place some of the driver’s status outputs to pins that can drive LEDs or other connectors where you can connect an oscilloscope or logic analyzer. You will have so many http://www.alteraforum.com/forum//images/icons/icon3.gif enlightning events just following the standard procedure that you will have no problems doing it once more with all your custom functions around it. 

 

Is there a demo design – even if it is binary only – for your DE3 board that can be used to verify that you don’t have any hardware issue with the chosen clock, reset, and DRAM connections?
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Valued Contributor III
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Hello Matthias, 

 

I followed your recommendations and finally it seems to work. Unfortunately neither the DE3 manual nor the HPC2 manual lose a word about the termination block. Reading through the internet, I found information about the Rup and Rdn PINs and that they have to be connected to VCCIO and GND. Nevertheless nobody mentioned which PINs exactly, so I had to try out some locations. Doing so and reducing the clock frequency to 200 MHz (the memory can handle 333 MHz) the example design worked. Using the system clock pin as clock for signaltap removed the timing errors. Even though I will have to look for another way, since 50 MHz is very low sampling frequency. Do you know of any way to improve the memory frequency? I would really like to reach the maximum frequency of the memory, since we really need every bit of performance there. There was no timing errors when I tried 233 MHz or 266 MHz, but the calibration failed, using these frequencies. Thank you. 

 

Best regards, 

Martin
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Valued Contributor III
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Hello Martin, 

 

See [here (http://www.altera.com/literature/hb/external-memory/emi.pdf#page=1219)] about the termination block and pins. We use two pins that are named RUP2 and RDN2 (located E25/D26 on our Arria II GX in 1152 pin package), and RUP2 is connected to 1.8 V via a 49.9 Ohm resistor, RDN2 to GND via another 49.9 Ohm resistor. The following are the only assignments in our QSF about them: 

 

set_location_assignment PIN_E25 -to termination_blk0~_rup_pad set_location_assignment PIN_D26 -to termination_blk0~_rdn_padYou will certainly find the right candidate pins on your Stratix III package on the DE3 board. If you haven’t already … :) 

 

Again, I suggest you work through Volume 6, Section 1–4 of the emi (http://www.altera.com/literature/hb/external-memory/emi.pdf#page=1251) covering a complete walkthrough of DDR2-HPC2/ALTMEMPHY with Stratix III. Don’t pass a step, don’t take shortcuts ;) And it should bring you 400 MHz (DDR2-800) given correct timing parameters. 

 

In the process of raising the memory frequency, you may have to find exact pin models, i.e. trace lengths, near and far end loads as well as termination resistors. I would assume that the HPC2 can operate at higher frequencies if it is working at half the frequency (and twice the data width), so you should try that option. 

 

My design on Arria II GX95 Grade 5, with just a rough pin model, gave no timing violation at 233 MHz but had a corner temperature problem at 266 MHz. In the lab, it worked at 266 MHz nevertheless and I got the calibration success and init_done. And this was done _including_ the SignalTap with a full-rate controller. I clock the SignalTap with the phy_clk, according to the following line in my QSF, so I think there should be no problems getting to 266 and even 333 MHz in your Stratix III: 

 

set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "ddr2_32bit:ddr2_32bit_inst|ddr2_32bit_controller_phy:ddr2_32bit_controller_phy_inst|phy_clk" -section_id auto_signaltap_0I know that one is tempted to start off with all parameters set to max performance, but this results in very slow to no development progress if you don’t hit the sweet spot of functionality with your first shot. Start with a slow clock and no other components, get comfortable with SignalTap, choose the right controller and bridge configuration, raise the frequency, fine-tune your memory model (CAS timing, etc.) and analog pin characteristics. 

 

Hope this helps, 

– Matthias
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Valued Contributor III
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Hello Matthias, 

 

Thank you for your help! I succeeded in implementing the HPC2 with my custom logic. After creating LogicLock-regions and manually reassigning a clock buffer, the timing problems disappeared. Now I have a weird problem on the hardware: 

 

Sometimes a read-burst is split into several smaller burst (I observed this in the rtl simulation too, but there it worked fine) and not all valid words contain valid data. As you can see in the first attached signaltap waveform, the marked burst is split and only the first 2 data beats are delivered. In the rtl simulation (I attached a modelsim waveform with exactly the same address, so you can compare it) all data beats are delivered. This does not always happen. As you can see later in the waveform. In the second signaltap waveform you can see, that the burst was split in 4 parts, but there is no problem with the data. Maybe you already saw these symptoms and can explain to me why this happens and how I can fix it. Thank your very much advance! 

 

Best regards, 

Martin 

 

EDIT: 

 

I also encountered bit errors on the read data. I am fairly sure that the written data is correct. The read data is sometimes correct and sometimes not.
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Valued Contributor III
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Hi, 

 

I forgot to mention, that I haven't derated the memory timings (tDH, tDS, tIH, tIS) yet. I just did it and will try the new settings. Can you tell me about the slew rates of the ddr pins? Do I have to set the slew rate according to the tutorial (e.g. CLK and CLK# = 1.5 V/ns (differential))? Or is it just for derating calculations and the slew rate of these pins should remain at 3? Thank your very much. 

 

Best regards, 

Martin 

 

EDIT: 

 

Derating improved the signal integrity, but the problem still persists.
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Valued Contributor III
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Hi, 

 

does anyone have an idea, what the problem with the bit errors could be? I tried the DE3 example design and it works fine. When I use the same settings for my design it doesn't work well. Bit errors occur every once in a while. Not always, but sometimes. I have no idea what else I should do. I tried everything already. Please help me! 

 

Best regards, 

Martin
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Valued Contributor III
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Hi, 

 

I made a funny observation this morning. I turned on the FPGA, uploaded the design and it worked well for a few minutes. No errors whatsoever. Then after a few minutes the error count goes up. Until it reaches the same error rate as before. So I assume that it has something to do with the temperature of the FPGA. But as I am concerned this shouldn't happen. Especially since the temperature is only about 43 °C (109 °F). Unfortunately I am not a electrical engineer, so I can hardly explain why this happens. 

 

Best regards, 

Martin
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