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Altera_Forum
Honored Contributor I
1,384 Views

DDR2 User Controlled Refresh

Hi, 

 

My name is Hardik Shah. I am using Cyc3 Dev board for my work. 

 

I have the following questions. I am using high performance controller. 

 

i) The document "External Memory Interface Handbook Volume 3 - DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide" says that it is possible to control the refresh using signal local_refresh_req. On page 7-8 it says that consecutive 9 refreshes can be given using this signal. On the other hand on page 7-17 it says that if user is using the above mentioned signal then he responsible for providing sufficient requests (one per 7.8 us). Can someone please clearify this? 

 

ii) In my desing, I enabled "User Auto Refresh" and stored 10000 integers into ddr2, waited for several minutes and read them all again. Though I intensionaly did not give any refresh during that time, I got the expected results. How? (I tested the program both with small data cache and without one. The whole code can fit into instruction cache) 

 

iii) In ddr2, each row of each bank has to be refreshed seperately or entire chip goes into refresh mode? 

 

iv) On page 9-3 the document says that refreshes can be issued in burst mode. If single refresh is enough to refresh entire chip, why would I want to issue unneccessary burst refreshes (which may consume lot of power) when my chip is already refreshed?
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7 Replies
Altera_Forum
Honored Contributor I
49 Views

i) SDRAM requires a refresh every 64ms. This is done a row at a time, usually there are 8192 rows so if you space these out evenly you need to do a refresh every 7.8us. However, JEDEC spec for SDRAM allows you to do up to 9 row refreshes back to back, thus allowing a longer period before doing another batch, which may help with efficiency in some systems 

ii) minutes is not that unusual under ideal conditions, tens of minutes would be. 

iii) refresh is done on a per row basis 

iv) only a row is refreshed, so i think what they mean by burst is doing up to 9 as mentioned above
Altera_Forum
Honored Contributor I
49 Views

Hi std_logic, 

 

Thanks for the information. The JEDEC specification says, "When CS, RAS and CAS are held LOW and WE HIGH at the rising edge of the clock, the chip enters the Refresh mode (REF)."  

(1) Is there any internal logic which supplies with the ROW numbers and informs the memory which ROW to refresh? 

 

(2) If yes, is there any way to control which ROW to refresh from outside? Though we have 8192 ROWs, we wont use them all. So only those ROWs are required to refresh which contain data. 

 

Best regards, 

Hardik
Altera_Forum
Honored Contributor I
49 Views

From a micron data sheet 

"The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command." 

 

I believe this is a just a sequential counter, so you cant refresh part of the memory. I'm not aware of any way around this.
Altera_Forum
Honored Contributor I
49 Views

SDRAM usually have a refresh controller, so You have to assert a special pin combination (e.g. CS,RAS,CAS low, WE high and a last address high), then the self-refresh of all the rows occours. I am not sure about the sequence I've mentioned, that was only an example.

Altera_Forum
Honored Contributor I
49 Views

Mobile DRAM has partial array refreshes, perhaps that is more suitable for your application.

Altera_Forum
Honored Contributor I
49 Views

Hi, 

 

Thanks for your answers. I could do the user controlled refresh on DDR2. But, now struck with another problem.  

 

We know that DDR memories work in a burst fashion. To describe in detail, check my settings in the images attached. 

 

1) I use the same data bit width, 32, for DDR2 HPC II local interface as well as the master connected to it.  

2) In the full rate mode both operate at the same frequency of 125 MHz. 

3) Number of DQs = 16. "memory Burst Length = 4" and "Maximum Local Interface Burst = 8". 

4) You can see in the image SOPC.bmp that I try to access the DDR2 from a component called tt_shared_ddr2. The component simply connects the instruction and data cache of the CPU (32 byte cache line, 32 byte burst) to the DDR2. 

5) For each "cache miss" burst of 8 is asked to the tt_shared_ddr2, which is simply forwarded to the DDR2. 

6) I tried both address mapings "chip-bank-row-col" and "chip-row-bank-col". 

 

now my question: 

 

When the data is asked in a burst fashion, the responce is only word by word. And there are >32 clock cycles between two "read_data_valid". 

 

According to the documentation, 16 bit DQs * 4 Beat burst = 64 bits of data. And that makes 2 "read_data_valid" back-to-back. I am using cyclone III development kit. 

 

Best regards, 

Hardik Shah
Altera_Forum
Honored Contributor I
49 Views

Hardik, 

 

I also tried doing the autorefresh using the local_auto_refresh_req signal but could not see any visible results. Did you do the same thing. Is there any setting we need to change? 

 

AR
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