I am having trouble setting up ddr2 memory for a micron MT47H32M16HR-25E single memory chip with Altera ALTMEMPHY with Quartus 11.1 and QSYSI have set all the timings to the data sheet from a close default (MT47H32M16CC-3). When I build the system it produces various pins on the epld to connect to DDR2 RAM. I have assumed the mem_clk pin is mem_clk_p as the other pin is labeled mem_clk_n I can only connect the mem_clk_p pin to a bidir as when I connect it to an output pin to drive the DDR2 RAM I get a warning message Error: The DDIO_OUT WYSIWYG primitive "........ir:DDR_CLK_OUT.ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_outa" feeding the pin "ddr2_clk_out_p" has multiple fan-outs My memory check software runs from onchip memory but as soon as I access the DDR2 memory Nios hangs at the instruction to access the memory 　 Thanks Neil
Thanks for the reply SocratesYes I connected up the mem_clk_p and mem_clk_n to the DDR2 memory. I was just confused that the Alters ALTMEMPHY called mem_clk_p mem_clk without the p. I have also got the memory running with Microtronix licensed DDR2 controller IP. Just confused why I could not get it going with the ALTMEMPHY controller. Especially as a number of other people on this forum have used the same memory chip successfully with ALTMEMPHY Neil
Yes thats a distinct possibility its not an easy science setting up all those parameters correct. I started with a micron MT47H32M16CC-3 to get in the right ball park and then adjusted the parameters to the micron datasheet.I have attached the setup screenshots I left the Board settings and Controller settings pages at the defaults as they seem a bit of a black art Thanks again for your help Neil
Are You running Nios using ddr2 memory clk? It should be 125MHz then. I'd offer to try half rate bridge (this will require double the burst length, so do it) and test the system.
Hi SocratesThanks for the advice I set it to half rate as you suggested and it all burst into life. I need to check now will my NIOS CPU be running at 125 MHz or 62.5MHz ( I am using the sysclk out of the ALTMEMPY to clock the system) If you could explain why you have to use half rate or point me to some online literature I would be very gratefull Still a great end to the year with a working design:D Thanks again Neil
Damn database error! Written a looong answer before :/ Ok shorted version:Available options: 1) Leave full rate (125MHz) and provide perfect timing constraints, because Nios above 100MHz can't run correctly. 2) Leave full rate, but add pipeline bridge and connect all peripherals to that bridge. 3) Use it as it is now with half rate bridge at 62.5MHz. As I said - Nios clocked above 100MHz must have perfect timing constrains.