Hi, my company developed a borad with ddr2 x36 sync sram(cypress CY7C1520KV18)
the SRAM is connected Altera arria V. in the megawizard there is only QDR sram controller available. i whould like to get a ref code and/or relevant documention on how to implement the phy level in the FPGA for that device. best regards or shoshaniLink Copied
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