04-17-2014 03:31 PM
Have anyone been able to control a DDR2 SDRAM using the UniPHY Megacore IP from Cyclone V??Im trying to do so, I have use this same memory with a Cyclone III before and im using the same circuit design, same time parameter, everything. But no matter how much I tried, the memory seem to not respond ( I tried 2 different FPGAS and 2 different memories) Do any one has some idea about this? Has anyone controlled a DDR2 with Cyclone V? Thanks all for the nice help, Bart
07-22-2014 01:46 AM
Helo,Do you have our Cyclone V dev kit? Did you try to run the simulation first using the generated example design? Make sure the PHY calibration is passing as well as the user mode (read / write). After that you may jump into hardware testing and you may use the EMIF toolkit to check if your design is working. Hope this helps.
08-01-2014 09:39 AM
Hello guys,I am also facing difficulties to get the DDR2 uniphy controller work. Calibration is failing at the last steps: "Write Calibration - Per-bit write deskew failure". (message from EMIF toolkit) Any idea what I should check?
10-30-2014 06:38 AM
I reduced the speed interface to 200MHz, I can validate the timing, but the calibration still fails.So that I can pass the calibration I've had to configure the "Advanced Clock Phase Control" parameter: "Additional Command And Clock Phase : 115 degrees". But then the timing analysis fails. Altera support answers was: Soft controller is not suppported for your speed grade 8 CycloneV (5CSEBA6U23C8). Very happy to know that at this step of the project...