Hi all, I'm new to DDR interfacing but I spent weeks trying to have UniPHY or ALTMEMPHY work with my DE-4 board, a 1GB SO-DIMM, and the stratix IV FPGA. No success yet.Firstly, the demo that comes from Terasic seems to work fine. the control panel application can read and write from the RAM, and the tutorial applications built by terasic for DDR2 access (built using ALTMEMPHY and SOPC builder) work as well, both when the ready binary is used or when I re-compile their source code and download the bitstream again. I am using QII 11.1, whereas their code seems to have been written using QII9.1 or something like that. Here is the problem: I would like just a simple test application, no SOPC or Qsys, no NIOS.. Just the DDR2 controller interface, and a test state machine with a "pass/fail" indication. Apparently both UniPhy and ALTMEMPHY can provide such "working examples". I tried both on my board, only to get a failing result. The parameters for the DDR2 memory, including timing, terminations, pin locations and signal levels, grouping, etc, were all COPIED from the working Terasic demo. I even tried running the TCL script for the DDR2 megafunction instead of copying the assignments. In all cases, my tests fail. I have no debug access to the pins to check voltage levels (at least not at 400MHz). I am sure there is something fundamental that I am missing in the set up, but I fail to see what it is. I just started a new project, instantiated DDR2 controller with ALTMEMPHY, put all parameters, pin assignments, and as required by the RAM I have (and the DE4 board). Then I rely on the Altera-furnished test driver to test the memory. I compile the example project, and download it. Is there anything missing here ? I noticed that the RAM has an I2C interface that is somehow interfaced to in the Terasic working project. However, I doubt this I2C bus is necessary if I know all of the timing and configuration parameters for the RAM. Can anyone see what I am missing ?
Hi:You are probably not doing the pll reconfiguration. With high speed DDR2 timing, you need to find the appropriate PLL phase setting for the read/write to work. This is discussed in the altmemphy documentation found at: http://www.altera.com/literature/ug/ug_altmemphy.pdf The altpll-recofig documentation is also required to understand the sequence. http://www.altera.com/literature/ug/ug_altpll_reconfig.pdf The Nios software, is probably doing this calibration at startup, so if you dig though the sample code you'll probably see it doing the PLL reconfiguration to adjust the read and write timing. The I2C interface allows the NIOS to read the ram information, letting you know how much ram is out there, what it's RAS/CAS latency is, etc. This is not strictly required if you know the info for the module you are using, but allows for adjustments for various modules. Regards Pete
Hi Anakha, I have checked Terasic's code line by line. There is no peculiar operations being done. Just Regular memory access by ANSI's memcpy function. Would it be possible that Altera's implementation for the memcpy (wherever the runtime library is located) is doing the reconfiguration transparently ? And that their example driver is not ? I am going to use Terasic's code as a template and build upon it, but I really see no reason why the example driver would fail for an identical configuration.