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Valued Contributor III
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DDR2 with Uniphy Calibration

Hello, 

 

I'm trying to get a DDR2 interface up and running. The hardware seems to work fine when I use the EMIF toolkit. Calibration and margining tests pass with flying colors. 

 

Now when I try to use memtest in SBT for Eclipse, my controller won't calibrate. I've verified this in Signaltap. The Qsys system is different so I'm guessing the issue is there but I don't see what's wrong that would cause this. 

 

I've attached screenshots of the EMIF toolkit and Signaltap showing initialization is done as well as memtest Signaltap showing calibration unfinished and the associated Qsys system. 

 

Does anyone have any ideas what might be wrong? Any help would be greatly appreciated! 

 

Thanks, 

Scott
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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

Have you solved this one yet? We are also having trouble getting the controller to calibrate when loaded in the Stratix V part. Which device are you targeting? 

 

Regards, 

Guy
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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

I've partially solved the calibration part on the Stratix IV I'm using. The key for me was the reset structure. If you signaltap the DDR interface and look at the resets, pll lock, and status signals (local_cal_success, local_cal_fail, local_init_done) then it could give you some indication of where the breakdown is happening. 

 

I've got a simple project with the avl clock coming out of the DDR2 interface driving the whole system. Now that works so I'm trying to separate the DDR2 clock domain from everything else using a clock crossing bridge. Still working through that now. 

 

If you throw your qsys file up, I'll take a quick peek to see if anything jumps out at me. I'll put my simple one up in case it can help you. Just change it to .qsys since the forum won't let me post that file type directly. 

 

Regards, 

Scott
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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

The afi_reset looping back to the clock crossing bridge looks a bit suspect to me.

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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

Hi BadOmen, 

 

Thank you for taking a look at my project. I took my own advice and used SignalTap on several of my reset signals and it looks like afi_reset was part of the problem. I couldn't find any examples that used a different clock domain for the DDR2 interface in Qsys so I was just trying to piece it together myself. You don't happen to have any experience getting the CSR to read so you can use the full functionality of the EMIF toolkit do you? :D 

 

I've attached the working qsys file, hopefully it can help someone avoid that mistake in the future. Not saying it's the best design but it does work. Change .txt to .qsys.  

 

Thanks again, 

Scott
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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

Unfortuantely I have not accessed the CSR port of the memory controller yet (wasn't aware that was already released :)) Since it's exposed I would assume the register map of that slave port is documented somewhere.

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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

The CSR port is referenced in the External Memory Interface Handbook on page 6-2 (1078/1266). I can't find the ports in Qsys, though the documentation implies that nothing is required by the user. I can see CSR signals when I browse around in the RTL viewer but they never come close to the JTAG interface. Perhaps it really hasn't been released. That would explain everything :rolleyes: At least I know it's not just me, thanks!

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Valued Contributor III
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Re: DDR2 with Uniphy Calibration

If it's in the GUI then it is probably released. I would assume you want to use the Avalon-MM slave if you want another master like Nios II for example to access the CSR, otherwise I would stick to the JTAG version. If there are tools already available from Altera that access this CSR port then I assume they expect to see a JTAG interface (for now at least). The JTAG connections won't be easily traced, I won't go into the details why but take my word for it :)

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