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Altera_Forum
Honored Contributor I
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DDR3 External Memory Interface Controller

Hello! 

 

Can anyone advise me as to where I can find the the signalling diagram at the Memory Interface for the DDR3 External Memory Interface (HPC II)? 

 

I also wanted to know whether, when I do bank-interleaving for reads, the controller completes the burst for each bank before giving the read response for the other banks? 

 

Similar information regarding writes would be appreciated. 

 

Thank you, 

Anand
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