Can i connect the pll_refclk input in the DDR3 ip core by using a PLL ip core. Does the pll_refclk input in the DDR3 core has to be provided by means of an oscillator.
You can connect it with the PLL IP but I think you need to close the timing issue due to that connection.
It's should be connected to the clock source pin.
You should refer to the EMIF User Guide in Chapter 6: DDR3 - Pin and Resource Planning.
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