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DDR3 IP internal Timing problem

SYou1
Beginner
ā€Ž02-27-2020 03:09 AM
315 Views

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BoonT_Intel
Moderator
ā€Ž02-28-2020 01:49 AM
190 Views

Hi Sir,

Yes the timing violation between MPFE port can be safely ignore. See this KDB for details šŸ˜ƒ

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

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SYou1
Beginner
ā€Ž02-28-2020 06:13 AM
190 Views

Thanks a lot!

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BoonT_Intel
Moderator
ā€Ž02-28-2020 07:29 AM
190 Views

You are welcome.

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