FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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DDR3 IP internal Timing problem

SYou1
Beginner
973 Views

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谢谢

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BoonT_Intel
Moderator
848 Views

Hi Sir,

Yes the timing violation between MPFE port can be safely ignore. See this KDB for details 😃

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd08142014_213.html

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SYou1
Beginner
848 Views

Thanks a lot!

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BoonT_Intel
Moderator
848 Views

You are welcome.

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