DDR3 IP internal Timing problem

[SYou1]

客户使用DDR3 IP的做了一个最小系统，使用了全部6个port，每个port时钟都不一样，现在每个时钟（都小于125Mhz）到IP内部的时钟都出现了时序问题。请问下IP内部是如何同步时钟的？是否能忽略

谢谢

[BoonT_Intel]

Hi Sir,

Yes the timing violation between MPFE port can be safely ignore. See this KDB for details 😃

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd08142014_213.html

[SYou1]

Thanks a lot!

[BoonT_Intel]

You are welcome.