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DDR3 IP internal Timing problem

SYou1
Beginner
304 Views

客户使用DDR3 IP的做了一个最小系统,使用了全部6个port,每个port时钟都不一样,现在每个时钟(都小于125Mhz)到IP内部的时钟都出现了时序问题。请问下IP内部是如何同步时钟的?是否能忽略

谢谢

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3 Replies
BoonT_Intel
Moderator
179 Views

Hi Sir,

Yes the timing violation between MPFE port can be safely ignore. See this KDB for details 😃

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

SYou1
Beginner
179 Views

Thanks a lot!

BoonT_Intel
Moderator
179 Views

You are welcome.

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