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DDR3 IP simulation error Error: (vsim-10000) Unresolved defparamreference to 'power_s

Altera_Forum
Honored Contributor II
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While simulatintg the DDR3 SDRAM Uniphy IP example desing I am getting below given Errors :- 

Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv(1621): Unresolved defparam reference to 'power_saving_exit_cycles' in hmc_inst.power_saving_exit_cycles.# Region: /ddr3_eg_example_sim/e0/if0/c0# ** Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv(1622): Unresolved defparam reference to 'mem_clk_entry_cycles' in hmc_inst.mem_clk_entry_cycles.# Region: /ddr3_eg_example_sim/e0/if0/c0# ** Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv(1623): Unresolved defparam reference to 'priority_remap' in hmc_inst.priority_remap.# Region: /ddr3_eg_example_sim/e0/if0/c0# ** Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv(1624): Unresolved defparam reference to 'enable_burst_interrupt' in hmc_inst.enable_burst_interrupt.# Region: /ddr3_eg_example_sim/e0/if0/c0# ** Error: (vsim-10000) ./..//submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv(1625): Unresolved defparam reference to 'enable_burst_terminate' in hmc_inst.enable_burst_terminate.# Region: /ddr3_eg_example_sim/e0/if0/c0# ** Error: (vsim-10000) ./..//submodules/ddr3_eg_example_sim_e0_if0_p0_acv_hard_memphy.v(676): Unresolved defparam reference to 'm_hphy_ac_rom_init_file' in hphy_inst.m_hphy_ac_rom_init_file.# Region: /ddr3_eg_example_sim/e0/if0/p0/umemphy# ** Error: (vsim-10000) ./..//submodules/ddr3_eg_example_sim_e0_if0_p0_acv_hard_memphy.v(677): Unresolved defparam reference to 'm_hphy_inst_rom_init_file' in hphy_inst.m_hphy_inst_rom_init_file.# Region: /ddr3_eg_example_sim/e0/if0/p0/umemphy 

 

 

The simulation is done as explained in the "emi.pdf" chapter 10 Simulating Memory IP  

Software used for simulation is ModelSim ALTERA STARTER EDITION 10.0c. 

So please let me know what could be the possible Fix to these Errors?
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Altera_Forum
Honored Contributor II
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Hi kushal.....i am facing the same problem in ALtera Max 10...Did you find any solution of this problem? Appreciate your feedback.

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