FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

DDR3 IP w/ QII_12.1 Uniphy Stratix V - Simulation - Outputs to Mem Components are X's

Altera_Forum
Honored Contributor I
898 Views

Hi, 

 

I'm upgrading a working (sim & hardware) Stratix III Uniphy DDR3 controller to Stratix V design using QII_12.1 . The IP I've generated is for a "Quarter-rate" controller (ie 800MHz to the DDR3 components but 200MHz to the FPGA application side).  

 

I've built the simulation up in Modelsim SE-64 10.1b using the supplied scripts, but all the outputs to the DDR3 component (mem_reset_n, mem_ras, mem_cas, etc.) are unknown or mostly unknown even after a complete reset. Please see attached JPEG of waveform. 

 

All the inputs to the Altera IP block's top are known at this point in the simulation, and this isn't the behavior of our earlier SIII design. I've submitted a service request but there's been no response yet. Has anybody had this same problem? 

 

-Bill
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
60 Views

Working now. I needed the input resets known at time 0, and to have the ucode (HEX files) located in the sim directory.

Reply