DDR3 SDRAM Controller with UniPHY ECC Status Registers

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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR3 SDRAM Controller with UniPHY ECC Status Registers

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Hello, I am using the DDR3 SDRAM Controller with UniPHY on a Cyclone V FPGA. I have Enabled the Hard External Memory Interface, ECC, and CSR bus.

I want to use the CSR bus to read the ECC status for monitoring purposes but have not been able to determine the correct register set.

According to the Reference Material, there seem to be 3 register sets, UniPHY, Soft Controller, and Hard Controller. When I read the registers I get data that corresponds to the first but only the latter two have ECC status registers.

Can anyone explain how to correctly access this information? This is critical for our design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf

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