FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5745 Discussions

DDR3 SDRAM Controller with UniPHY ECC Status Registers

VCham
New Contributor I
112 Views

Hello, I am using the DDR3 SDRAM Controller with UniPHY on a Cyclone V FPGA. I have Enabled the Hard External Memory Interface, ECC, and CSR bus. 

I want to use the CSR bus to read the ECC status for monitoring purposes but have not been able to determine the correct register set. 

According to the Reference Material, there seem to be 3 register sets, UniPHY, Soft Controller, and Hard Controller. When I read the registers I get data that corresponds to the first but only the latter two have ECC status registers. 

Can anyone explain how to correctly access this information? This is critical for our design.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.p...

0 Kudos
0 Replies
Reply