Honored Contributor II
12-12-2012 03:55 AM
Hi all,I have a question in designing DDR3 ip core: - When designed DDR3 interface, I forgot to pull up and pull down RUP/RDN dedicated pins in DDR3 funtion banks. So, can I compile project with DDR3 Ip core successfully and the project can run correctly without OCT (on-chip calibration termination)? And I'm using Stratix IV FPGA. Thanks for reading and I'm very appreciated for any answer.