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Honored Contributor I
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DDR3 SDRAM HPC ip core, about OCT and RUP/RDN pins.

Hi all, 

 

I have a question in designing DDR3 ip core:  

 

- When designed DDR3 interface, I forgot to pull up and pull down RUP/RDN dedicated pins in DDR3 funtion banks. So, can I compile project with DDR3 Ip core successfully and the project can run correctly without OCT (on-chip calibration termination)? 

 

And I'm using Stratix IV FPGA. 

 

Thanks for reading and I'm very appreciated for any answer.
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