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DDR3 UNIPHY Master/Slave PLL/DLL's

Altera_Forum
Honored Contributor II
867 Views

Are therre any consequencies to setting up two DDR3 UNIPHY interfaces one a master PLL/DLL and the other a slave PLL/DLL? Are the individual nios processors able to perform all calibration independent of each other using the same PLL/DLL?  

 

Are there any gotcha's not in the External Memory Interfaces guide? The EMI guide seems to suggests no impact to the operation of the PHY.
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2 Replies
Altera_Forum
Honored Contributor II
98 Views

The purpose of this feature is as you describe. There should be no issues.

Altera_Forum
Honored Contributor II
98 Views

winfrees, 

I think thera are some limitations for sharing PLL/DLL in a master/salve UniPhy design. Please refer Chapter 4: Implementing Multiple Memory Interfaces Using UniPHY (p. 4-2) 

in External Memory Interface Handbook Volume 6, Section II. 

 

"To share the PLLs and DLLs, ensure that the controllers are on the same or adjacent  

side of the device and the PLL and DLL are running at the same memory-clock  

frequency. ..." 

 

I'm using two UniPhy controllers where each of them is configured as master. I have connected a 8GB UDIMM module on top 

and bottom of Stratix iv (EP4SGX110) device. It was not possible to share PLL and DLL within a master/slave configuration. Quartus did not fit the design. 

Obviously sharing is only viable if both controllers are on the same or adjacent  

side of the device. 

Are there any other experiences? I would use a linear address space within one clock domain for both modules. Using two masters is not the best solution 

because ther is more effort in synchronization and also more device resources needed. 

 

Jens
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