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DDR3 ip controller

Altera_Forum
Honored Contributor II
799 Views

Hi, 

 

I am working on DDR3 uniphy IP controller. I have generated IP controller and added Timing parameters asper the datasheet and generated it. I opened the example design as my top module and did pin assignment, run the tcl. I am doing the time quest analysis. I am getting setup time violation in 10 paths inside the example design. can any please suggest me how to remove these set up violations. 

Here i am attaching the setup violations paths and report. 

 

Thanks & Regards,
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2 Replies
Altera_Forum
Honored Contributor II
85 Views

Did you also run all the timing constraint files? The IP comes with a few SDC files that often have the wrong paths. This makes some of the synchronizers not get picked up by TimeQuest and because of that some paths wind up killing the synthesis. Often fake paths. 

 

What I did was to first create a task in the SDC file to mark the reset synchronizers: 

proc rstsync {path} { 

puts "Searching for Reset Synchronizer with path $path" 

set_false_path -to  

[add_to_collection  

[get_pins -nowarn -compatibility_mode -nocase $path|a*]  

[get_pins -nowarn -compatibility_mode -nocase $path|clrn]  

 

# Then I found the reset synchronizers and labeled them: 

rstsync {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*} 

rstsync {*|ureset_*|reset_reg[*]} 

 

# Then each time it complained I looked at the RTL that it complained and saw it was usually a two flop synchronizer that had no false path. So i added a false path for each one: 

set_false_path -to [get_pins -compatibility_mode {mem_ip_inst|mem_ip_inst|p0|umemphy|uread_datapath|read_buffering[*]*read_enable_r|*}] 

set_false_path -to [get_pins -compatibility_mode {mem_ip_inst|mem_ip_inst|p0|umemphy|uread_datapath|read_buffering[*]*read_valid_r|*}] 

 

 

The names will change from IP to IP. These were the ones I used.
Altera_Forum
Honored Contributor II
85 Views

Hi, 

 

This issue i have solved by reducing the memory clock speed to below 300MHz. Before entering Memory parameters we should check the maximum memory speed grade of our FPGA using altera memory spec estimator. 

 

Thanks & regards, 

C. Ashok reddy
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