DDR3 with Uniphy (Half rate mode with burst legnth 2 not supported?)

[Altera_Forum]

Hi all, 

I am working with a "DDR3 SDRAM Controller with UniPHY" megafunction created in Quartus 15.0.0.  My avalon-MM interface rate is half. All my transactions are a burst of size two (avl_size == 2).  I'm seeing strange things in simulation. Basically, the data returned (on the avalon side) on my read bursts are almost correct. However, the ddr3 commands generated by the core are fully correct, and the data returned on the dq bus is fully correct. So there's something funny happening between the memory bus and the avl interface.   I checked several times to make sure I'm following all the rules of the interface. So, I started digging into the modules generated by megawizard and I found this in mymodule_p0_read_datapath.sv  // ******************************************************************************************************************* // VALID PREDICTION // Read request (afi_rdata_en) is generated on the AFI clock domain (pll_afi_clk). // Read data is captured on the read_capture_clk domain (output clock from I/O).  // The purpose of valid prediction is to determine which read_capture_clk cycle valid data will be returned to the core // after the request is issued on pll_afi_clk; this is essentially the latency between read request seen on  // AFI interface and valid data available at the output of ALTDQ_DQS. // The clock domain crossing between pll_afi_clk and read_capture_clk is handled by a FIFO (uread_valid_fifo). // The pll_afi_clk controls the write side of the FIFO and the read_capture_clk controls the read side. // The pll_afi_clk writes into the FIFO on every clock cycle. When there is no read request, it writes a 0; // when there is a read request, it writes a 1 (refer to as a token) into the FIFO. // The read_capture_clk reads from the FIFO every clock cycle, whenever it reads a token, it means that valid data // is available during that cycle. Each token represents 1 cycle of valid data. // In full rate, BL=2, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle // In full rate, BL=4, 1 read results in 2 AFI cycles of valid data, controller asserts afi_rdata_en for 2 cycles // In full rate, BL=8, 1 read results in 4 AFI cycles of valid data, controller asserts afi_rdata_en for 4 cycles // in half rate, bl=2, not supported // In half rate, BL=4, 1 read results in 1 AFI cycle of valid data, controller asserts afi_rdata_en for 1 cycle // In half rate, BL=8, 1 read results in 2 AFI cycle of valid data, controller asserts afi_rdata_en for 2 cycles // In full rate, 1 afi_rdata_en cycle = 1 token // In half rate, 1 afi_rdata_en cycle = 2 tokens  Does this mean I can't do burst reads of size two when running in half rate mode? How can that be?