I am using DE5aNET-DDR4 to develop a design. It has a DDR4 controller. The memory clocks of the DDR4 that we have used, are 1200Mhz and 1000Mhz in Quarter; that is, 300Mhz and 250Mhz for the emif user clocks. It works, but sometimes needs to reset several times. Is it a problem in calibration or parmeter settings? Thanks.
Again, I suggest you contact Terasic and get an DDR4 example design from them. Then compare your design with their example design (especially all DDR4 IP parameters setting) and see if any different that will causing this problem.