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Altera_Forum
Honored Contributor I
837 Views

DMA Controller Core and data alignment

Hi, 

 

I have a problem with the DMA Controller Core which I can't understand. 

 

My system has a NIOS/f core (with unused MPU, 4Kb caches, 32 bytes data cache line size) connected to a SDRAM, a DMA controller and a clock crossing bridge. 

The DMA controller's master ports are connected to the SDRAM and the clock crossing bridge. The DMA controller has burst enabled with n=8. 

The clock crossing bridge is connected to a custom peripheral acting as a 

memory. The clocking bridge has burst enabled with n=8. 

All data busses are 32bits wide. 

The custom peripheral does not support bursts. It is accessed 8 times in a row by the DMA engine. 

 

What I'm trying to is to transfer data from the custom peripheral to the SDRAM by using the DMA. 

This only works fine if the receiving array (of unsigned longs) is aligned on 

an 8-bytes boundary (instead of 4-bytes boundary). If not, the DMA engine aligns the writen data on an 8-bytes boundary, swaps every pair of values and writes outside the receiving array (which from time to time corrups other data and crashes the software) . 

 

Why is this alignment apparently needed ? 

There must be an error somewhere in my configuration but I can't find where. 

Does anyone have a hint where I should start looking for ? 

 

Thanks, 

P9
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Altera_Forum
Honored Contributor I
68 Views

The problem seems to be located in the SDRAM controller, which does not like odd local start burst addresses (with, in my case, burst length=2). 

As the performance loss is not excessive without bursts, I will just skip them for the time being. 

 

P9
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