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DMA Controller in burst + Avalon MM PCIe results in data corruption.

Altera_Forum
Honored Contributor I
1,052 Views

I am having some trouble with Stratix and the DMA Controller in Burst mode and the Avalon MM PCIe bridge. 

 

When I start a 4k byte transfer with a SRC address of 0x****_9910 and DEST address of 0x****_A910 ... where the DMA controller is performing a DDR -> DDR move in the RC, I get unpredicable results. DMA controller is set for 4k burst length and Doubleword transfers. 

 

One failure is the last part of the DMA is not written to the desination buffer. ( see attachement ) 

One failure is wrong data written around the 4k boundary crossing. 

 

If I start at address of 0x****_9900 and cross the 4k boundary the test passes .  

If I start at address of 0x****_9910 and do not cross the 4k boundary the tests passes. 

 

Does any one know if the Avalon PCIe bridge has to have certain address when a burst transfer crosses a 4k boundary ? 

 

Thanks, Bob. 

 

Also: I can't find the logic that performs the 4k boundary crossing ( ie splits a transaction into two transactions to avoid crossing the 4k boundary ) Could that logic reside in the Hard PCIe IP ?
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Altera_Forum
Honored Contributor I
79 Views

I am looking at reproducing on an X86 Platform ... any advice on the driver to use and C compiler to use for running on X86 PC ?

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